Biomedical sensors operate under low supply voltage, in low frequency domains, and require low power consumption. This paper proposes a new power-efficient, low-pass and band-pass fully differential biquad suitable for bio-signal acquisition, based on Folded Gain Boosting Source-Follower (FGB-SF). This solution does not require a Common-Mode Feedback (CMFB) and it offers a wide tuning range. Implemented using 0.18 μm TSMC technology, it achieves the lowest power consumption reported in the literature (0.46 nW), a high Dynamic Range (DR) of 43.8 dB, and an IIP3 of 6.55 dBm with 250 Hz bandwidth. Post-layout simulations demonstrate stability under Montecarlo and PVT variations. The occupied area is only 69.5 μm x 51.3 μm and exibits the lowest FOM compared with the state of the art.

This paper introduces an innovative approach to designing a mismatched current mirror with a fully unbalanced output, significantly reducing the minimum supply voltage requirements for Regulated Cascode Current Mirror (RCCM) Physical Unclonable Functions (PUFs). Leveraging body-driven feedback mechanisms, the proposed circuit reliably operates with supply voltages as low as 0.3V, maintaining stable power consumption through a reference bias current. The resulting PUF achieves remarkable energy efficiency, consuming only 0.3 fJ per bit, without compromising statistical performance. It exhibits a response bias of 49.42%, a reliability of 99.483%, and a uniqueness of 50.176%. Validation of this novel approach is conducted through simulations and measurements on a 130nm CMOS test-chip, considering a nominal supply voltage of 0.3V, ±10% supply voltage variations, and a temperature range from 0°C to 75°C. Rigorous experimental verification on 20 chip samples, along with detailed explanations of design methodologies, underscores the robustness and practicality of the proposed Body-PUF design. Comparative analyses against state-of-the-art literature reveal that the Body-PUF outperforms previous PUF designs in Figures of Merit (FOM), making it promising for real-world authentication scenarios. Its outstanding trade-off between performance and practicality positions it as a compelling solution for secure applications, including Internet of Things (IoT) devices and other security-critical systems.

Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra models, because high-order Volterra terms require summing multiple products of the input signal. We propose a generalized complex Volterra model based on one relaxation of Volterra theory: all the nonlinear monomial terms in the model are considered separately, even if they correspond to a single real coefficient in complex Volterra theory. This produces more accurate models, though with a larger number of coefficients. We thus extensively prune the model by means of OMP and OBS techniques. The resulting models have fewer coefficients and/or better accuracy than conventional Volterra models, resulting in a significantly improved accuracy-complexity trade-off. These results are validated in the experimental calibration of a commercial IF amplifier. The resulting model achieves the same accuracy, with 9 free parameters and 34 multiplications, as the standard Volterra model with 12 parameters and 266 multiplications, resulting in a 25% reduction in the number of parameters, and an 87% reduction in the number of multipliers.

The Switched-Resistor (S-R) technique is becoming more and more interesting to implement low-voltage low-power active- RC filters with high tuning range and front-end amplifiers for biomedical circuits and systems. This approach exploits MOS switches driven by a duty-cycle-controlled clock signal to achieve tunability of the equivalent resistance and, hence, of the RC time constant. Since S-R circuits can be considered as linear periodically time variant (LPTV) systems with sampled outputs, we exploit the theory of the adjoint (inter-reciprocal) network in order to develop a detailed model of the cyclostationary noise involved in this kind of circuits. The proposed model allows to gain insight into the different noise sources and transfer functions involved, highlighting the circuit parameters on which the cyclostationary noise depends. Validation of the proposed model has been carried out by comparing analytical results against periodic noise simulations referring to a commercial 130nm CMOS process. The validation activity has confirmed the good accuracy of the proposed noise model and provided some useful design guidelines to optimize the noise performance of S-R circuits.

High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less filters are important for minimizing the chip area footprint. In this paper, we present the design of a 6th-order inductor-less 10GHz low-pass filter implemented in the STMicroelectronics SiGe BiCMOS55 process. It can be used as anti-aliasing filter for conventional 30GS/s digitizers or at the output of a 40GS/s ATI digitizer. We exploit positive feedback to synthesize the active inductor based on a stacked topology, minimizing the number of current branches, and thus power consumption. Analysis and design guidelines for the biquad are presented. The filter exhibits a bandwidth of 10GHz with a power consumption of 43mW, a THD of −45dB and an SNR of 43dB with an input amplitude of 710mV peak-to-peak differential. Extensive corner and Monte Carlo post-layout simulations have been carried out to highlight the robustness of the circuit to PVT and mismatch variations. Experimental results have confirmed very good agreement between measured and simulated performance, validating the proposed design flow.

In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110μW thus confirming the advantages of the proposed approach.

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology.

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Post layout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74-μW power consumption for the high-speed design and a maximum frequency of 10 GHz with 53-μW power consumption for the minimum PDP design.

In this paper we present a gain enhancement technique for very low-voltage deep sub-micron amplifiers based on the use of a CCH-based negative impedance converter. Relaxed specifications on the current conveyor allow an easy implementation of this technique in a sub-1 V environment, where common topologies such as the cascode and the differential pair cannot be used. An example implementation in a 65-nm CMOS technology, using plusmn0.35 V supply voltage and a simple 6-transistor CCH topology, shows a 15.5-dB gain enhancement with a good robustness against process variations.

Pipeline analog-to-digital converters (ADC) are widely used to achieve high resolution and moderately high sampling frequency. In typical implementations, linearity is often limited by capacitor mismatch and finite amplifier gain. The impact of these non ideal effects on the overall linearity of the ADC has been addressed in this paper, obtaining a model to estimate total harmonic distortion (THD), given capacitors' sizing and amplifiers' gain. This model enables the designer to analyze the impact of error sources in each stage separately, and to perform Monte Carlo simulations. In this way, design rules can be obtained to properly size each multiplying digital-to-analog converter (MDAC) in the first stages of the design process.

A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-based MMIC, expressed in terms of principal components, is presented. A statistical model has been extracted for 0.1 mum GaAs HEMT devices and MMIC's. Validation of the model is presented, based on principal component analysis and statistical hypothesis testing

A behavioral model of a sample-and-hold circuit is presented, focused on the distortion due to the nonlinear switch on-resistance. A simplified expression for third-order harmonic distortion has been derived, by using a quadratic MOS model where body effect is neglected, and it has been extended to the case of a transmission gate switch. Both the behavioral model and the distortion estimation have been validated by comparison with Cadence simulations, and very low errors have been obtained over a wide range of circuital and signal parameters

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f/sub T/ silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2/sup 23/-1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.