Attention is a crucial construct in Interactive Information Retrieval (IIR) activities and has become an area of growing interest among CHIIR researchers. Despite this importance, explicit definitions are rare. Many studies refer to “attention” without specifying which process or aspect is under examination, and often operationalize it using practical indicators (e.g., eye fixations, dwell time, cursor traces, interaction logs) without a clear conceptual framework guiding measurement choices, raising concerns about the comparability of findings. This paper reviews how attention has been defined, operationalized, and measured in CHIIR publications from the conference’s inception in 2016 through 2025. We searched the ACM Digital Library for "attention" within CHIIR proceedings, finding 296 results. After filtering and using semantic similarity, we narrowed it to 45 relevant papers, from which 19 were selected for in-depth review based on their clear relevance to attention. Drawing on theoretical frameworks and empirical findings from psychology and cognitive science, we analyze how CHIIR researchers define and apply the concept of attention in various contexts. Our review uncovers a variety of interpretations, aspects, and measurement approaches to attention, which reflect broader challenges in bridging cognitive theory and information interaction research. We discuss key issues underlying these differing uses of the term “attention,” and outline possible directions for advancing conceptual clarity and methodological robustness of attention research within CHIIR. We hope this perspective paper raises researchers’ awareness of the need to clearly define attention, thereby promoting greater rigor and reproducibility in future IIR studies.

Relevance assessment is central to interactive information retrieval, yet most studies focus on judgment outcomes rather than underlying cognitive processes. Eye-tracking reveals how individuals allocate visual attention, but spatial gaze distribution measures only capture limited aspects of gaze behavior. In this study, we use a previously collected eye-tracking dataset to provide a multidimensional analysis of visual attention and cognitive load during document evaluation, examining spatial gaze distribution, fixation density, visual search dynamics, and pupil-based measure of cognitive load. Our results show that irrelevant documents, that are objectively irrelevant and judged as such, were scanned quickly, with shorter fixations, higher saccade rates, simpler scanpaths, and lower cognitive load. In contrast, relevant or topical documents, and documents left unjudged, showed longer fixations, slower saccades, focused inspection, greater scanpath complexity, and higher cognitive load. Our findings highlight that relevance assessment is a dynamic process shaped by interactions between document properties and individual judgments.

Understanding how users perform map-based tasks is essential for improving map design and supporting efficient spatial decision-making. Eye-tracking and pupil-based measures provide objective insights into visual search organization and cognitive load. Using a previously collected eye-tracking dataset, we examined differences in scanpath complexity, average inter-saccadic direction change (AISDC), and pupil-based cognitive load between high- and low-efficiency task performance during location-finding and route-planning on cartographic and satellite maps. Each sub-task was divided into three temporal phases for analysis. All participants completed all tasks. Results showed that scanpath complexity reflected how visual search organization varied with both task type and map representation. However, task efficiency was not associated with AISDC; instead, AISDC varied significantly across task phases, reflecting temporal changes in visual scanning behavior. Furthermore, pupil-based cognitive load was not significantly related to task efficiency. These findings deepen our understanding of visual strategies and cognitive demands, highlighting their importance in navigation tool design.

The rapidly-changing deep learning landscape presents a unique opportunity for building inference accelerators optimized for specific datacenter-scale workloads. We propose Full-stack Accelerator Search Technique (FAST), a hardware accelerator search framework that defines a broad optimization environment covering key design decisions within the hardware-software stack, including hardware datapath, software scheduling, and compiler passes such as operation fusion and tensor padding. In this paper, we analyze bottlenecks in state-of-the-art vision and natural language processing (NLP) models, including EfficientNet and BERT, and use FAST to design accelerators capable of addressing these bottlenecks. FAST-generated accelerators optimized for single workloads improve Perf/TDP by 3.7× on average across all benchmarks compared to TPU-v3. A FAST-generated accelerator optimized for serving a suite of workloads improves Perf/TDP by 2.4× on average compared to TPU-v3. Our return on investment analysis shows that FAST-generated accelerators can potentially be practical for moderate-sized datacenter deployments.

The importance of irregular applications such as graph analytics is rapidly growing with the rise of Big Data. However, parallel graph workloads tend to perform poorly on general-purpose chip multiprocessors (CMPs) due to poor cache locality, low compute intensity, frequent synchronization, uneven task sizes, and dynamic task generation. At high thread counts, execution time is dominated by worklist synchronization overhead and cache misses. Researchers have proposed hardware worklist accelerators to address scheduling costs, but these proposals often harden a specific scheduling policy and do not address high cache miss rates. We address this with Minnow, a technique that augments each core in a CMP with a lightweight Minnow accelerator. Minnow engines offload worklist scheduling from worker threads to improve scalability. The engines also perform worklist-directed prefetching, a technique that exploits knowledge of upcoming tasks to issue nearly perfectly accurate and timely prefetch operations. On a simulated 64-core CMP running a parallel graph benchmark suite, Minnow improves scalability and reduces L2 cache misses from 29 to 1.2 MPKI on average, resulting in 6.01x average speedup over an optimized software baseline for only 1% area overhead.

Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures, gate-oxide wearout, and transient faults are becoming increasingly common. In order to overcome these issues and develop robust design techniques for large-market silicon ICs, it is necessary to rely on accurate failure analysis frameworks which enable design houses to faithfully evaluate both the impact of a wide range of potential failures and the ability of candidate reliable mechanisms to overcome them. Unfortunately, while failure rates are already growing beyond economically viable limits, no fault analysis framework is yet available that is both accurate and can operate on a complex integrated system. To address this void, we present CrashTest, a fast, high-fidelity and flexible resiliency analysis system. Given a hardware description model of the design under analysis, CrashTest is capable of orchestrating and performing a comprehensive design resiliency analysis by examining how the design reacts to faults while running software applications. Upon completion, CrashTest provides a high-fidelity analysis report obtained by performing a fault injection campaign at the gate-level netlist of the design. The fault injection and analysis process is significantly accelerated by the use of an FPGA hardware emulation platform. We conducted experimental evaluations on a range of systems, including a complex LEON-based system-on-chip, and evaluated the impact of gate-level injected faults at the system level. We found that CrashTest is 16-90x faster than an equivalent software-based framework, when analyzing designs through direct primary I/Os. As shown by our LEON-based SoC experiments, CrashTest exhibits emulation speeds that are six orders of magnitude faster than simulation.