Varactors in RF CMOS processes often have significantly lower Q- factor ($Q_{VAR}$) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q,$Q_{T} < Q_{VAR}$, and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in$Q_{T}$. The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger$Q_{VAR}$. Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM$_{T}$of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM$_{T}$of −194.2 dBc/Hz.

The popularity of Deep Neural Networks (DNNs) has led to many DNN accelerator architectures, which typically focus on the on-chip storage and computation costs. However, much of the energy is spent on accesses to off-chip DRAM memory. While emerging resistive memory technologies such as MRAM, PCM, and RRAM can potentially reduce this energy component, they suffer from drawbacks such as low endurance that prevent them from being a DRAM replacement in DNN applications. In this paper, we examine how DNN accelerators can be designed to overcome these limitations and how emerging memories can be used for off-chip storage. We demonstrate that through (a) careful mapping of DNN computation to the accelerator and (b) a hybrid setup (both DRAM and an emerging memory), we can reduce inference energy over a DRAM-only design by a factor ranging from 1.12× on EfficientNetB7 to 6.3× on ResNet-50, while also increasing the endurance from 2 weeks to over a decade. As the energy benefits vary dramatically across DNN models, we also develop a simple analytical heuristic solely based on DNN model parameters that predicts the suitability of a given DNN for emerging-memory-based accelerators.

Although in-band full-duplexing (IBFD) has long been implemented in various communication media, it was only recently that an IBFD solution was presented for broadband power line communications (BB-PLCs). The maximum attainable echo suppression using this solution is, however, limited by the dynamic range of the analog-to-digital converter (ADC). To counter this critical constraint, we propose echo cancellation in the analog domain, while persisting with a low-complexity frequency domain digital echo estimation. By formulating an expression for the number of ADC bits lost in IBFD over a conventional half-duplex operation, we show that the ADC dynamic range is no longer a limiting factor for our solution. We further extend our solution to present an analog cancellation method for multiple-input multiple-output IBFD BB-PLC systems. Finally, we present simulation results of echo cancellation and data rate gains obtained under realistic in-home BB-PLC settings, to demonstrate that our solution is capable of doubling bidirectional transfer rates in a large number of the tested network conditions.

We introduce in-band full duplexing (IBFD) for broadband power line communication (BB-PLC) systems. Inspired by the use of IBFD in digital subscriber lines, Ethernet, cable communication, and recently in wireless communication, we investigate the constraints and requirements for a successful IBFD implementation in BB-PLC. We propose a two-stage IBFD structure consisting of an initial analog isolation using an active hybrid circuit, and a simplified mixed-domain digital echo cancellation procedure to suppress the self-interference. Furthermore, we enhance the digital cancellation filter to better adapt to linear periodically time-varying channel conditions, commonly encountered in PLC scenarios. We evaluate our solution under diverse power line channel and noise conditions to examine the overall data rate gains that can be achieved. Last, we extend IBFD to multiple-input multiple-output (MIMO) BB-PLC systems that enable faster and/or more robust data transmission.

A fully-integrated LNA in 0.18/xm CMOS simultaneously achieves high gain, low noise figure (NF), good third-order input intercept linearity (IIP3), and low DC bias current consumption: 19 dB, 2.4 dB, -14.2 dBm and 1.3 mA, respectively, from a 1.2 V supply. The single-ended LNA uses a common-gate common-source (CG-CS) topology and operates at 5.4 GHz for WLAN applications. Using gm-boosting, current-reuse and transformer-feedback techniques, the LNA mitigates several design issues seen in the widely used common-source common-source current-reuse (CS-CS) LNAs and improves the IIP3 of CG-CS schemes by 6 dB, without increasing power and area consumption.

An area-efficient U-shaped slow-wave coplanar waveguide (U-SCPW) in a standard 0.18 μm CMOS process is presented. Compared to a conventional straight line CPW (S-CPW), it provides a more compact layout because of its approximate 1:1 aspect ratio. Measured results show that it has a quality factor and phase velocity comparable to its straight-line counterpart with measured Q ~ 30 at 23 GHz.

A delay generation technique applied to loop-bandwidth enhancement of frequency synthesizers is proposed for faster switching. PMOS transistors are used to provide large resistances and a diode-connected PMOS device generates the switch gate-bias voltage to reduce delay variations over process. An integer-N PLL employing the above technique for bandwidth enhancement is designed and simulated at 2.4GHz. It has a phase noise of -123dBc/Hz @ 1MHz offset. The lock time is 40mus, and the tuning range is 200MHz

A fully integrated 5-6GHz differential VCO derived from the classical Clapp topology is presented in 180nm CMOS. The Clapp architecture and its characteristics are reviewed, and the location of critical portions of the circuit such as the LC-tank and varactors is discussed. The use of a Clapp VCO topology allows a larger voltage swing, which improves spectral purity and phase noise. The use of a symmetrical inductor for differential operation results in a higher Q with lower area, while providing common-mode noise rejection. The VCO achieves a simulated phase noise of -98dBc/Hz @ 100kHz & -123.1dBc/Hz @ 1MHz offsets, and draws 5mA from a 1.8V power supply. A high tuning range of 18% and FOM of 189dBc/Hz are reported. Finally, system-level simulations of a frequency synthesizer for the IEEE 802.11a bands using the Clapp VCO are presented