Hyperspectral imaging is an excellent tool to remotely analyze the Earth from in-orbit devices. Satellites capture these images containing vast information about the ground pixels. To optimize storage and transmission speeds, compression is often performed onboard the satellite. To that end, algorithms such as the CCSDS 123.0-B-2 are implemented on FPGAs, enabling this process in an efficient and fast manner. Single-Event Upsets (SEU) are commonplace in this scenario, e.g. bit flips in the FPGA’s configuration memory which can catastrophically alter the algorithm’s output. In this paper, we propose a fault tolerance technique for this specific case. The compression core is checked periodically by running a golden model designed to excite the full internal datapath based on a synthetic image. A failure in this check will trigger a reconfiguration of the compression core. Results show better detection rates than Dual Modular Redundancy (DMR) at a fraction of the resource cost, proving this technique as a viable alternative. Furthermore, other algorithms with similar processing flows might benefit as well from this technique.

Since the advent of air and space-borne flight, remotely sensed images of the Earth’s surface have changed how the world is perceived: meteorology, navigation, surveillance, and environmental sciences are some of the areas, in which technology has fundamentally changed. Hyperspectral images extend the possibilities even further by capturing wavelengths outside the visible spectrum. This is particularly valuable for target detection, often performed using drones, satellites, or other unmanned aerial vehicles (UAVs). In many applications such as surveillance and security, it is critical to perform this detection in real-time. Response times can be optimized by performing these calculations on-board, which introduces additional power, radiation tolerance, and resource constraints. To that end, embedded devices such as field-programmable gate arrays (FPGAs) are ideal candidates, as their reprogrammable logic allows for a great degree of acceleration while having low power consumption. In this article, a real-time FPGA implementation of the linearly constrained minimum variance (LCMV) algorithm for target classification is presented. First, an analysis is performed to explore the most parallelizable and accurate numerical methods that fit within the resource constraints of FPGAs, and finally selecting LDL decomposition. Then, hardware modules for LCMV classification are designed in SystemVerilog, focusing on incremental correlation matrix computation and a solver for LDL matrix decomposition. The proposed implementation on a radiation-tolerant Xilinx XQRKU060 is compared to an embedded CUDA-accelerated graphics processing unit (GPU) and an embedded central processing unit (CPU), showing turnaround time improvements of$7.25\times $and$825\times $, respectively. It runs$15\times $faster than real-time, with sufficient margin to accommodate the next generation of hyperspectral sensors.

In hyperspectral image analysis one of the most important tasks is target detection, requiring the execution of algorithms with high computational complexity. Recently, research efforts have focused on on-board real-time target detection to provide timely responses for swift decisions. Therefore, it is necessary to use a technology that provides the performance needed for real-time target detection, and at the same time meets the satellite payload requirements. Field-programmable gate arrays (FPGAs) have very interesting properties in terms of performance, size and power consumption, which have become the standard option for on-board processing. In this letter, we present a hardware optimized implementation for FPGAs of the automatic target detection and classification algorithm (ATDCA) using the Gram–Schmidt (GS) method for orthogonalization purposes. The ATDCA-GS algorithm is directly coded using VHDL and verified on a Virtex-7 XC7VX690T FPGA using real hyperspectral data (collected by Hyperspectral Digital Imagery Collection Experiment (HYDICE) sensor and by NASA’s Airborne Visible/Infrared Imaging Spectrometer (AVIRIS)) and a synthetic image. Experimental results demonstrate that our hardware version of the ATDCA-GS algorithm outperforms previous implementations (multicore processors, GPUs and accelerators) in both computation time (obtaining real-time performance) and power consumption, demonstrating the suitability of FPGAs for this purpose.

Hyperspectral images are a useful remote sensing tool that often reaches hundreds of megabytes in size. The CCSDS 123.0-B-2 is a recent algorithm that achieves lossless and near-lossless compression of hyperspectral images by introducing a configurable maximum error over its predecessor CCSDS 123.0-B-1. In this article, a field-programmable gate array (FPGA) implementation of the revised standard that works in real-time is presented. We have developed an extremely pipelined and fast core in VHDL, that is able to process a sample per cycle at over 250 MHz, working eight times faster than in real time for the Airborne Visible-Infrared Imaging Spectrometer-Next Generation (AVIRIS-NG) sensor. New dependencies in the revised standard are avoided by using a novel sample ordering called frame interleaved by diagonal. The predictor stage has been designed to work in this order, and two reorder buffers encapsulate it to be band interleaved by pixel compliant. Predictor data are encoded using a novel FPGA implementation of the CCSDS 123.0-B-2 hybrid coder. The modules are tested and verified on a Virtex-7 VC709 board. For medium (256 bands$\times4096$frames$\times512$samples) and large ($512\times 4096\times 1024$) images, the core occupies, respectively, 14% and 50% of an XQRKU060 FPGA.

Segmented and pipelined execution has been a staple of computing for the past decades. Operations over different values can be carried out at the same time speeding up computations. Hyperspectral image compression sequentially processes samples, exploiting local redundancies to generate a predictable data stream that can be compressed. In this article, we take advantage of a low complexity predictive lossy compression algorithm which can be executed over an extremely long pipeline of hundreds of stages. We can avoid most stalls and maintain throughput close to the theoretical maximum. The different steps operate over integers with simple arithmetic operations, so they are especially well-suited for our FPGA implementation. Results on a Virtex-7 show a maximum frequency of over 300 MHz for a throughput of over 290 MB/s, with a space-qualified Virtex-5 reaching 258 MHz, being five times as fast as the previous FPGA designs. This shows that a modular pipelined approach is beneficial for these kinds of compression algorithms.