Demo Data from VLDB 2026 / reviewers in the wild / expert
M. Spaziani Brunella
dblp:211/2902 · also Marco Spaziani Brunella
· DBLP profile ↗
5ranked-venue papers
2as first author
2since 2021 · last 2023
0000-0001-8448-0432ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 3 · 2 first-author · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
3 papers |
Software-defined and programmable networks · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Reconfigurable computing and FPGAs · 60% Hardware accelerators and domain-specific architectures · 40% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Software-defined and programmable networks
programmable data plane |
1.1 | 3 | 2022 | Faster Software Packet Processing on FPGA NICs with eBPF Program Warping · USENIX ATC 2022 FlowBlaze: Stateful Packet Processing in Hardware · NSDI 2019 hXDP: Efficient Software Packet Processing on FPGA NICs · OSDI 2020 |
Reconfigurable computing and FPGAs › FPGA-based network processing
FPGA-based network interface |
0.4 | 1 | 2020 | hXDP: Efficient Software Packet Processing on FPGA NICs · OSDI 2020 |
Software-defined and programmable networks › programmable data plane
stateful packet processing |
0.4 | 1 | 2019 | FlowBlaze: Stateful Packet Processing in Hardware · NSDI 2019 |
Hardware accelerators and domain-specific architectures
network accelerator |
0.3 | 2 | 2022 | Faster Software Packet Processing on FPGA NICs with eBPF Program Warping · USENIX ATC 2022 FlowBlaze: Stateful Packet Processing in Hardware · NSDI 2019 |
Methods — techniques the papers use, named apart from their topics
eBPF · 1.1XDP · 0.9stateful processing · 0.8FPGA-based packet processing · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | CPU-free Computing: A Vision with a BlueprintabstractSince the inception of computing, we have been reliant on CPU-powered architectures. However, today this reliance is challenged by manufacturing limitations (CMOS scaling), performance expectations (stalled clocks, Turing tax), and security concerns (microarchitectural attacks). To re-imagine our computing architecture, in this work, we take a more radical, but pragmatic approach and propose to eliminate the CPU with its design baggage from data center computing. We integrate three primary pillars of computing, i.e., networking, storage, and computing, into a single, self-hosting, unified CPU-free Data Processing Unit (DPU) called Hyperion. The elimination of the CPU from computing necessitates re-thinking our computing, networking, and storage abstractions, and tackle the associated challenges which we sketch in this paper. We share the blueprint of our work-in-progress, Hyperion's hardware and software stack, and seek feedback. Animesh Trivedi, M. Spaziani Brunella |
HotOS | 2 |
| 2022 | Faster Software Packet Processing on FPGA NICs with eBPF Program Warping
Marco Bonola, Giacomo Belocchi, Angelo Tulumello, M. Spaziani Brunella, Giuseppe Siracusano, Giuseppe Bianchi 0001, Roberto Bifulco |
USENIX ATC | 4 |
| 2020 | hXDP: Efficient Software Packet Processing on FPGA NICs
M. Spaziani Brunella, Giacomo Belocchi, Marco Bonola, Salvatore Pontarelli, Giuseppe Siracusano, Giuseppe Bianchi 0001, Aniello Cammarano, Alessandro Palumbo, Luca Petrucci, Roberto Bifulco |
OSDI | 1 |
| 2019 | Foreshadow-VMM: Feasibility and Network PerspectiveabstractOn August 14, 2018, a new set of vulnerabilities collectively named “L1 terminal fault” were announced. Systems with microprocessors utilizing out-of-order execution could allow unauthorized disclosure of information residing in the L1data cache, by tweaking the virtual memory abstraction. The vulnerability was therein mentioned for three different scenarios. In this demo-paper, we provide practical evidence about the feasibility of the most complex “VMM” case of an attacker residing in a Virtual Machine (VM), and targeting information leakage from the host OS and other independent VMs. M. Spaziani Brunella, Giuseppe Bianchi 0001, Sara Turco, Francesco Quaglia, Nicola Blefari-Melazzi |
NetSoft | 1 |
| 2019 | FlowBlaze: Stateful Packet Processing in Hardware
Salvatore Pontarelli, Roberto Bifulco, Marco Bonola, Carmelo Cascone, M. Spaziani Brunella, Valerio Bruschi, Davide Sanvito, Giuseppe Siracusano, Antonio Capone, Michio Honda, Felipe Huici |
NSDI | 5 |