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Zhuliang Yao

dblp:211/7232 · DBLP profile ↗
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9ranked-venue papers
2as first author
5since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 7 · 2 first-author · 4 since 2021Graphics, computer vision, multimedia, augmented reality and games · 7 · 2 first-author · 4 since 2021Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
9 papers
Deep learning architectures and training · 26% Efficient and distributed learning · 22% Representation and self-supervised learning · 15%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Hardware accelerators and domain-specific architectures · 68% Reconfigurable computing and FPGAs · 30% GPUs and heterogeneous computing · 3%

Topics — the 30 heaviest of 33, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA accelerator
1.222025
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity · FPGA 2019
Machine learning › Efficient and distributed learning
model compression
1.032025
Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity · FPGA 2019
Balanced Sparsity for Efficient DNN Inference on GPU · AAAI 2019
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
sparse neural network acceleration
0.912025
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Computer vision › Image recognition and object detection
image classification
0.822023
iCLIP: Bridging Image Classification and Contrastive Language-Image Pre-training for Visual Recognition · CVPR 2023
Swin Transformer V2: Scaling Up Capacity and Resolution · CVPR 2022
Computer vision › Vision and language › vision-language model
CLIP
0.712023
iCLIP: Bridging Image Classification and Contrastive Language-Image Pre-training for Visual Recognition · CVPR 2023
Computer vision › Vision and language
vision-language pretraining
0.712023
iCLIP: Bridging Image Classification and Contrastive Language-Image Pre-training for Visual Recognition · CVPR 2023
Machine learning › Transfer learning and domain adaptation › zero-shot learning
zero-shot classification
0.712023
iCLIP: Bridging Image Classification and Contrastive Language-Image Pre-training for Visual Recognition · CVPR 2023
Machine learning › Efficient and distributed learning › model compression › pruning
structured pruning
0.622025
Balanced Sparsity for Efficient DNN Inference on GPU · AAAI 2019
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Machine learning › Representation and self-supervised learning › representation learning › unsupervised representation learning › self-supervised representation learning › masked modeling
masked image modeling
0.612022
SimMIM: a Simple Framework for Masked Image Modeling · CVPR 2022
Machine learning › Efficient and distributed learning › large-scale learning
model scaling
0.612022
Swin Transformer V2: Scaling Up Capacity and Resolution · CVPR 2022
Machine learning › Deep learning architectures and training › scaling laws
neural network scaling
0.612022
Swin Transformer V2: Scaling Up Capacity and Resolution · CVPR 2022
Machine learning › Representation and self-supervised learning › representation learning › unsupervised representation learning
self-supervised representation learning
0.612022
SimMIM: a Simple Framework for Masked Image Modeling · CVPR 2022
Machine learning › Deep learning architectures and training › transformer › vision transformer
swin transformer
0.612022
Swin Transformer V2: Scaling Up Capacity and Resolution · CVPR 2022
Machine learning › Deep learning architectures and training › transformer
vision transformer
0.612022
Swin Transformer V2: Scaling Up Capacity and Resolution · CVPR 2022
Machine learning › Representation and self-supervised learning › pre-training › visual pre-training
vision transformer pre-training
0.612022
SimMIM: a Simple Framework for Masked Image Modeling · CVPR 2022
Machine learning › Deep learning architectures and training › normalization
batch normalization
0.512021
Cross-Iteration Batch Normalization · CVPR 2021
Machine learning › Deep learning architectures and training
normalization
0.512021
Cross-Iteration Batch Normalization · CVPR 2021
Machine learning › Optimization for machine learning
small-batch training
0.512021
Cross-Iteration Batch Normalization · CVPR 2021
Machine learning › Deep learning architectures and training › attention mechanism › attention network
non-local neural network
0.412020
Disentangled Non-local Neural Networks · ECCV (15) 2020
Machine learning › Efficient and distributed learning › model compression › sparsity
structured sparsity
0.412019
Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity · FPGA 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator
0.412019
Balanced Sparsity for Efficient DNN Inference on GPU · AAAI 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.412019
Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity · FPGA 2019
Hardware accelerators and domain-specific architectures › sparsity exploitation
sparse inference acceleration
0.412019
Balanced Sparsity for Efficient DNN Inference on GPU · AAAI 2019
Computer vision › Face, body and person analysis
person re-identification
0.312017
Orientation Invariant Feature Embedding and Spatial Temporal Regularization for Vehicle Re-identification · ICCV 2017
Computer vision › Face, body and person analysis › person re-identification
vehicle re-identification
0.312017
Orientation Invariant Feature Embedding and Spatial Temporal Regularization for Vehicle Re-identification · ICCV 2017
Machine learning › Transfer learning and domain adaptation
zero-shot transfer
0.212023
iCLIP: Bridging Image Classification and Contrastive Language-Image Pre-training for Visual Recognition · CVPR 2023
Computer vision › Video understanding and tracking
action recognition
0.212022
Swin Transformer V2: Scaling Up Capacity and Resolution · CVPR 2022
Computer vision › Segmentation and scene understanding
semantic segmentation
0.212022
Swin Transformer V2: Scaling Up Capacity and Resolution · CVPR 2022
Machine learning › Representation and self-supervised learning › representation learning
disentangled representation learning
0.112020
Disentangled Non-local Neural Networks · ECCV (15) 2020

Methods — techniques the papers use, named apart from their topics

structured pruning · 1.7fine-grained sparsity · 1.7multi-task learning · 0.7knowledge augmentation · 0.7self-supervised pretraining · 0.6scaled cosine attention · 0.6residual post normalization · 0.6pixel regression · 0.6masked patch prediction · 0.6log-spaced continuous position bias · 0.6weight pruning · 0.4fine-grained pruning · 0.4compressed sparse banks · 0.4bank-balanced sparsity · 0.4balanced sparsity · 0.4
YearPublicationVenuePosition
2025 Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference
abstract
With the explosive growth in the number of parameters in deep neural networks (DNNs), sparsity-centric algorithm and hardware designs have become critical for low-latency AI serving systems. However, the inherent randomness in pruning methods often leads to fragmented data access and irregular computation patterns in sparse matrices, resulting in significantly reduced hardware efficiency. Addressing the balance between the ‘randomness’ required to maintain model accuracy and the ‘regularity’ needed for efficient hardware design is crucial for realizing effective sparse computing in AI. This article proposes a fine-grained structured sparsity (FSS) paradigm. The pruned sparse matrices in this paradigm exhibit characteristics of ‘local randomness’ and ‘global regularity’. This dual-feature design allows AI accelerator hardware based on the FSS paradigm to maintain both high model accuracy and efficient hardware design. We implemented this novel accelerator on the Xilinx Alveo U280 and validated our concept across three different AI models, including CNN, RNN, and LLM, demonstrating performance that significantly outperforms prior methods.
Chen Zhang 0001, Shijie Cao, Guohao Dai 0001, Chenbo Geng, Zhuliang Yao, Wencong Xiao, Yunxin Liu 0001, Ming Wu 0007, Guangyu Sun 0003, Zhigang Ji, Runsheng Wang, Ru Huang 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2023 iCLIP: Bridging Image Classification and Contrastive Language-Image Pre-training for Visual Recognition
abstract
This paper presents a method that effectively combines two prevalent visual recognition methods, i.e., image classification and contrastive language-image pre-training, dubbed iCLIP. Instead of naïve multi-task learning that use two separate heads for each task, we fuse the two tasks in a deep fashion that adapts the image classification to share the same formula and the same model weights with the language-image pre-training. To further bridge these two tasks, we propose to enhance the category names in image classification tasks using external knowledge, such as their descriptions in dictionaries. Extensive experiments show that the proposed method combines the advantages of two tasks well: the strong discrimination ability in image classification tasks due to the clean category labels, and the good zero-shot ability in CLIP tasks ascribed to the richer semantics in the text descriptions. In particular, it reaches 82.9% top-1 accuracy on IN-1K, and mean-while surpasses CLIP by 1.8%, with similar model size, on zero-shot recognition of Kornblith 12-dataset benchmark. The code and models are publicly available at https://github.com/weiyx16/iCLIP.
Yixuan Wei, Yue Cao 0001, Zheng Zhang 0022, Houwen Peng, Zhuliang Yao, Zhenda Xie, Han Hu 0001, Baining Guo
CVPR5
2022 Swin Transformer V2: Scaling Up Capacity and Resolution
abstract
We present techniques for scaling Swin Transformer [35] up to 3 billion parameters and making it capable of training with images of up to 1,536x1,536 resolution. By scaling up capacity and resolution, Swin Transformer sets new records on four representative vision benchmarks: 84.0% top-1 accuracy on ImageNet- V2 image classification, 63.1 / 54.4 box / mask mAP on COCO object detection, 59.9 mIoU on ADE20K semantic segmentation, and 86.8% top-1 accuracy on Kinetics-400 video action classification. We tackle issues of training instability, and study how to effectively transfer models pre-trained at low resolutions to higher resolution ones. To this aim, several novel technologies are proposed: 1) a residual post normalization technique and a scaled cosine attention approach to improve the stability of large vision models; 2) a log-spaced continuous position bias technique to effectively transfer models pre-trained at low-resolution images and windows to their higher-resolution counterparts. In addition, we share our crucial implementation details that lead to significant savings of GPU memory consumption and thus make it feasi-ble to train large vision models with regular GPUs. Using these techniques and self-supervised pre-training, we suc-cessfully train a strong 3 billion Swin Transformer model and effectively transfer it to various vision tasks involving high-resolution images or windows, achieving the state-of-the-art accuracy on a variety of benchmarks. Code is avail-able at https://github.com/microsoft/Swin-Transformer.
Han Hu 0001, Yutong Lin, Zhuliang Yao, Zhenda Xie, Yixuan Wei, Yue Cao 0001, Zheng Zhang 0022, Li Dong 0004, Furu Wei, Baining Guo
CVPR4
2022 SimMIM: a Simple Framework for Masked Image Modeling
abstract
This paper presents SimMIM, a simple framework for masked image modeling. We have simplified recently proposed relevant approaches, without the need for special designs, such as block-wise masking and tokenization via discrete VAE or clustering. To investigate what makes a masked image modeling task learn good representations, we systematically study the major components in our framework, and find that the simple designs of each component have revealed very strong representation learning performance: 1) random masking of the input image with a moderately large masked patch size (e.g., 32) makes a powerful pre-text task; 2) predicting RGB values of raw pixels by direct regression performs no worse than the patch classification approaches with complex designs; 3) the prediction head can be as light as a linear layer, with no worse performance than heavier ones. Using ViT-B, our approach achieves 83.8% top-1 fine-tuning accuracy on ImageNet-1K by pre-training also on this dataset, surpassing previous best approach by +0.6%. When applied to a larger model with about 650 million parameters, SwinV2-H, it achieves 87.1% top-1 accuracy on ImageNet-1K using only ImageNet-1K data. We also leverage this approach to address the data-hungry issue faced by large-scale model training, that a 3B model (Swin V2-G) is successfully trained to achieve state-of-the-art accuracy on four representative vision benchmarks using 40× less labelled data than that in previous practice (JFT-3B). The code is available at https://github.com/microsoft/SimMIM.
Zhenda Xie, Zheng Zhang 0022, Yue Cao 0001, Yutong Lin, Jianmin Bao, Zhuliang Yao, Qi Dai 0001, Han Hu 0001
CVPR6
2021 Cross-Iteration Batch Normalization
abstract
A well-known issue of Batch Normalization is its significantly reduced effectiveness in the case of small mini-batch sizes. When a mini-batch contains few examples, the statistics upon which the normalization is defined cannot be reliably estimated from it during a training iteration. To address this problem, we present Cross-Iteration Batch Normalization (CBN), in which examples from multiple recent iterations are jointly utilized to enhance estimation quality. A challenge of computing statistics over multiple iterations is that the network activations from different iterations are not comparable to each other due to changes in network weights. We thus compensate for the network weight changes via a proposed technique based on Taylor polynomials, so that the statistics can be accurately estimated and batch normalization can be effectively applied. On object detection and image classification with small mini-batch sizes, CBN is found to outperform the original batch normalization and a direct calculation of statistics over previous iterations without the proposed compensation technique. Code is available at https://aka.ms/cbn.
Zhuliang Yao, Yue Cao 0001, Shuxin Zheng, Gao Huang 0001, Stephen Lin 0001
CVPR1
2020 Disentangled Non-local Neural Networks
Minghao Yin, Zhuliang Yao, Yue Cao 0001, Xiu Li 0001, Zheng Zhang 0022, Stephen Lin 0001, Han Hu 0001
ECCV (15)2
2019 Balanced Sparsity for Efficient DNN Inference on GPU
abstract
In trained deep neural networks, unstructured pruning can reduce redundant weights to lower storage cost. However, it requires the customization of hardwares to speed up practical inference. Another trend accelerates sparse model inference on general-purpose hardwares by adopting coarse-grained sparsity to prune or regularize consecutive weights for efficient computation. But this method often sacrifices model accuracy. In this paper, we propose a novel fine-grained sparsity approach, Balanced Sparsity, to achieve high model accuracy with commercial hardwares efficiently. Our approach adapts to high parallelism property of GPU, showing incredible potential for sparsity in the widely deployment of deep learning services. Experiment results show that Balanced Sparsity achieves up to 3.1x practical speedup for model inference on GPU, while retains the same high model accuracy as finegrained sparsity.
Zhuliang Yao, Shijie Cao, Wencong Xiao, Chen Zhang 0001, Lanshun Nie
AAAI1
2019 Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity
abstract
Neural networks based on Long Short-Term Memory (LSTM) are widely deployed in latency-sensitive language and speech applications. To speed up LSTM inference, previous research proposes weight pruning techniques to reduce computational cost. Unfortunately, irregular computation and memory accesses in unrestricted sparse LSTM limit the realizable parallelism, especially when implemented on FPGA. To address this issue, some researchers propose block-based sparsity patterns to increase the regularity of sparse weight matrices, but these approaches suffer from deteriorated prediction accuracy. This work presents Bank-Balanced Sparsity (BBS), a novel sparsity pattern that can maintain model accuracy at a high sparsity level while still enable an efficient FPGA implementation. BBS partitions each weight matrix row into banks for parallel computing, while adopts fine-grained pruning inside each bank to maintain model accuracy. We develop a 3-step software-hardware co-optimization approach to apply BBS in real FPGA hardware. First, we propose a bank-balanced pruning method to induce the BBS pattern on weight matrices. Then we introduce a decoding-free sparse matrix format, Compressed Sparse Banks (CSB), that transparently exposes inter-bank parallelism in BBS to hardware. Finally, we design an FPGA accelerator that takes advantage of BBS to eliminate irregular computation and memory accesses. Implemented on Intel Arria-10 FPGA, the BBS accelerator can achieve 750.9 GOPs on sparse LSTM networks with a batch size of 1. Compared to state-of-the-art FPGA accelerators for LSTM with different compression techniques, the BBS accelerator achieves 2.3 ~ 3.7x improvement on energy efficiency and 7.0 ~ 34.4x reduction on latency with negligible loss of model accuracy.
Shijie Cao, Chen Zhang 0001, Zhuliang Yao, Wencong Xiao, Lanshun Nie, Dechen Zhan, Yunxin Liu 0001, Ming Wu 0007
FPGA3
2017 Orientation Invariant Feature Embedding and Spatial Temporal Regularization for Vehicle Re-identification
abstract
In this paper, we tackle the vehicle Re-identification (ReID) problem which is of great importance in urban surveillance and can be used for multiple applications. In our vehicle ReID framework, an orientation invariant feature embedding module and a spatial-temporal regularization module are proposed. With orientation invariant feature embedding, local region features of different orientations can be extracted based on 20 key point locations and can be well aligned and combined. With spatial-temporal regularization, the log-normal distribution is adopted to model the spatial-temporal constraints and the retrieval results can be refined. Experiments are conducted on public vehicle ReID datasets and our proposed method achieves state-of-the-art performance. Investigations of the proposed framework is conducted, including the landmark regressor and comparisons with attention mechanism. Both the orientation invariant feature embedding and the spatio-temporal regularization achieve considerable improvements.
Zhongdao Wang, Luming Tang, Xihui Liu, Zhuliang Yao, Shuai Yi, Shengjin Wang, Hongsheng Li 0001, Xiaogang Wang 0001
ICCV4