CAD exploration is important for designing FPGA interconnect topologies. It includes two steps: first, design a model with some parameters that can express as much architecture space. Second, use CAD flow to analyze the described interconnect architecture. In this paper, we present a new interconnect model, named INTB (Interconnect Block). At a logical position, one INTB is adopted to represent all related routing resources and hierarchical parameters are designed to simplify description. Compared with existing CB-SB model, INTB model can support more interconnect features of modern FPGA, such as various types of wire segment and complex connections. These features can improve FPGA routing ability. For the application of INTB model, two modifications are made in CAD flow: one is generation of routing resource graph (RRG). A tile-based method is proposed to generate RRG from parameters. The other is cost computing during routing process. Two strategies are applied respectively for cost estimation of short and curve wire segment, which do not exist in CB-SB model. INTB model and CAD improvement are implemented in VTR 8.0. The experiments consist of two parts. First, INTB model is adopted to re-describe CB-SB architectures to verify its description capacity. After CAD flow, average difference of routing area and timing between two models is about 4% and 5%. Second, INTB model is used to explore architecture space with modern FPGA features. Experimental results show obvious performance enhancement, over 10% in some benchmarks.

Modern FPGA has complex interconnect, like curve wires and two-level local muxs (global wires -> block input pins). Existing interconnect model (CB-SB) cannot describe these routing fabrics, hindering CAD exploration of modern FPGA.

As the capacity of FPGA increases, FPGA placers that adopt Simulated Annealing (SA) algorithm take more and more runtime. To solve this problem, this paper presents HCAS, a Hybrid algorithm Combining Analytical method and SA. There are three modifications in HCAS: (1) In global placement, faster and better result is realized by modified analytical algorithm. (2) In detailed placement, proper tradeoff is made between quality and runtime through improvement of SA. (3) Optimization workload of timing and wirelength is reasonably assigned between global and detailed placement according to algorithm features. HCAS is implemented in the newest VPR. Compared to VPR placer, it obtains a speedup of 11.1x, with 3% shorter wirelength and 5% smaller critical path delay. Compared to other analytical-based hybrid placers, HCAS achieves greater speedup and enhancement of placement quality is similar or better.