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Utsav Banerjee

dblp:213/0925 · DBLP profile ↗
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10ranked-venue papers
5as first author
7since 2021 · last 2025
0000-0001-7949-4178ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 5 · 4 first-author · 3 since 2021Systems, architecture and hardware · 3 · 1 first-author · 2 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 70% Electronic design automation · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › formal verification
equivalence checking
0.812024
QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Emerging computing paradigms › quantum computer architecture
quantum circuit verification
0.812024
QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Emerging computing paradigms
quantum computer architecture
0.812024
QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Emerging computing paradigms › quantum computer architecture
quantum error correction
0.212024
QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

decision diagrams · 0.8
YearPublicationVenuePosition
2025 A Unified Hardware Accelerator for Fast Fourier Transform and Number Theoretic Transform
abstract
The Number Theoretic Transform (NTT) is an indispensable tool for computing efficient polynomial multiplications in post-quantum lattice-based cryptography. It has strong resemblance with the Fast Fourier Transform (FFT), which is the most widely used algorithm in digital signal processing. In this work, we demonstrate a unified hardware accelerator supporting both 512-point complex FFT as well as 256-point NTT for the recently standardized NIST post-quantum key encapsulation and digital signature algorithms ML-KEM and MLDSA respectively. Our proposed architecture effectively utilizes the arithmetic circuitry required for complex FFT, and the only additional circuits required are for modular reduction along with modifications in the control logic. Our implementation achieves performance comparable to state-of-the-art ML-KEM / ML-DSA NTT accelerators on FPGA, thus demonstrating how an FFT accelerator can be augmented to support NTT and the unified hardware can be used for both digital signal processing and post-quantum lattice-based cryptography applications.
Rishabh Shrivastava, Chaitanya Prasad Ratnala, Durga Manasa Puli, Utsav Banerjee
ICASSP4
2024 Energy-Efficient and Secure Clustering with Post-Quantum DTLS in Wireless Sensor Networks
abstract
In this work, the standard Datagram Transport Layer Security (DTLS) protocol is integrated with the widely used Low-Energy Adaptive Clustering Hierarchy (LEACH) routing protocol for secure clustering in wireless sensor networks (WSNs) with pre-quantum and post-quantum authenticated key exchange, referred to as DTLS-LEACH and pqDTLS-LEACH respectively. Strong security guarantees of the DTLS protocol ensure that various security requirements of WSNs are satisfied. Detailed analysis of cryptographic computation and communication costs is presented using elliptic curve cryptography (pre-quantum) and lattice-based cryptography (post-quantum), followed by a system-level energy model. An efficient certificate public key caching scheme is also proposed which reduces handshake computation and communication costs by 30% and 50% respectively, while having 2.5× smaller storage requirement.
Utsav Banerjee
ISCC1
2024 QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding
abstract
Quantum computing has proven to be capable of accelerating many algorithms by performing tasks that classical computers cannot. As quantum algorithms and implementations grow more complex, the need for rigorous circuit verification becomes critical, ensuring correct compilation and enhancing circuit fidelity through error correction and assertions. In this paper, we propose QuBEC, a Decision Diagram-based quantum equivalence checking approach, that requires less latency compared to existing techniques, while accounting for circuits with quantum error correction redundancy. QuBEC reduces verification time on benchmark circuits by up to 443×, while the number of Decision Diagram nodes required is reduced by up to 798.31×, compared to state-of-the-art strategies. The proposed QuBEC framework can contribute to the advancement of quantum computing by enabling faster and more efficient verification of quantum circuits, paving the way for the development of larger and more complex quantum algorithms.
Navnil Choudhury, Utsav Banerjee, Abdullah Ash-Saki, Kanad Basu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2023 Privacy-Preserving Edge Computing from Pairing-Based Inner Product Functional Encryption
abstract
Pairing-based inner product functional encryption provides an efficient theoretical construction for privacy-preserving edge computing secured by widely deployed elliptic curve cryptography. In this work, an efficient software implementation framework for pairing-based function-hiding inner product encryption (FHIPE) is presented using the recently proposed and widely adopted BLS12-381 pairing-friendly elliptic curve. Algorithmic optimizations provide$\approx 2.6\times$and$\approx 3.4\times$speedup in FHIPE encryption and decryption respectively, and extensive performance analysis is presented using a Raspberry Pi 4B edge device. The proposed optimizations enable this implementation framework to achieve performance and ciphertext size comparable to previous work despite being implemented on an edge device with a slower processor and supporting a curve at much higher security level with a larger prime field. Practical privacy-preserving edge computing applications such as encrypted biomedical sensor data classification and secure wireless fingerprint-based indoor localization are also demonstrated using the proposed implementation framework.
Utsav Banerjee
GLOBECOM1
2022 Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic
abstract
Quantum computing furnishes exponential speed up over classical computing in specific areas. For example, Shor’s algorithm can factor two numbers in a polynomial time complexity. Thus, many encryption algorithms that rely on large number factorization are potentially vulnerable to quantum computers. In order to address this, the National Institute of Standard and Test (NIST) has organized a competition to evaluate several post quantum cryptography (PQC) algorithms, that are secure from the attacks from quantum computers. Several of these lattice-based PQC encryption algorithms are based on Learning With Errors (LWE) computation. Conversely, LWE is the heaviest computation in a classical computer, which incurs significant portion of the latency overhead for the entire encryption algorithm. In this paper, we design an optimized quantum circuit for LWE computation. The proposed quantum circuit does not need any ancillary qubits and scales efficiently and easily if there are more qubits available on a higher qubit quantum computer.
Utsav Banerjee, Kanad Basu
ICCD2
2021 Securing Embedded Medical Devices using Dual-Factor Authentication
abstract
This work provides an analysis of dual-factor authentication protocol for securing low-power medical devices. The dual-factor protocol incorporates voluntary physical action-based authentication in addition to traditional cryptographic methods for adding an extra layer of security. Along with touch signals, we propose and analyze the use of electromyographic (EMG) signals obtained from hand gestures for the second factor authentication. We demonstrate the feasibility of touch and EMG signals for dual-factor authentication by prototyping the medical device using off-the-shelf components. We also develop energy models for all these protocols, and analyze their overheads compared to traditional single-factor cryptographic authentication.
Saurav Maji, Utsav Banerjee, Samuel H. Fuller, Rabia Tugce Yazicigil, Anantha P. Chandrakasan
CBMS2
2021 Leaky Nets: Recovering Embedded Neural Network Models and Inputs Through Simple Power and Timing Side-Channels - Attacks and Defenses
abstract
With the recent advancements in machine learning theory, many commercial embedded microprocessors use neural network (NN) models for a variety of signal processing applications. However, their associated side-channel security vulnerabilities pose a major concern. There have been several proof-of-concept attacks demonstrating the extraction of their model parameters and input data. But, many of these attacks involve specific assumptions, have limited applicability, or pose huge overheads to the attacker. In this work, we study the side-channel vulnerabilities of embedded NN implementations by recovering their parameters using timing-based information leakage and simple power analysis side-channel attacks. We demonstrate our attacks on popular microcontroller platforms over networks of different precisions, such as floating point, fixed point, and binary networks. We are able to successfully recover not only the model parameters but also the inputs for the above networks. Countermeasures against timing-based attacks are implemented and their overheads are analyzed.
Saurav Maji, Utsav Banerjee, Anantha P. Chandrakasan
IEEE Internet Things J.2
2020 Efficient Post-Quantum TLS Handshakes using Identity-Based Key Exchange from Lattices
abstract
Identity-Based Encryption (IBE) is considered an alternative to traditional certificate-based public key cryptography to reduce communication overheads in wireless sensor networks. In this work, we build on the well-known lattice-based DLP-IBE scheme to construct an ID-based certificateless authenticated key exchange for post-quantum Transport Layer Security (TLS) handshakes. We also propose concrete parameters for the underlying lattice computations and provide detailed implementation results. Finally, we compare the combined computation and communication cost of our ID-based certificate-less handshake with the traditional certificate-based handshake, both using lattice-based algorithms at similar postquantum security levels, and show that our ID-based handshake is 3.7× more energy-efficient, thus highlighting the advantage of ID-based key exchange for post-quantum TLS.
Utsav Banerjee, Anantha P. Chandrakasan
ICC1
2020 Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor
abstract
Post-quantum cryptography (PQC) is currently a growing area of research and NIST PQC Round 2 schemes are being actively analyzed and optimized for both security and efficiency. In this work, we repurpose the cryptographic accelerators in an energy-efficient pre-quantum TLS crypto-processor to implement post-quantum key encapsulation schemes SIKE, Frodo and ThreeBears and signature scheme SPHINCS+. We utilize the modular arithmetic unit inside the elliptic curve cryptography accelerator to implement SIKE, while we use the AES-256 and SHA2-256 hardware primitives to substitute SHA3-256 and SHAKE-256 computations and accelerate the other three protocols. We accelerate the most computationally expensive components of these PQC protocols in hardware, thereby achieving up to an order of magnitude improvement in energy-efficiency over software implementations.
Utsav Banerjee, Siddharth Das, Anantha P. Chandrakasan
ISCAS1
2017 eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things
abstract
In the fast growing world of the Internet of Things (IoT), security has become a major concern. Datagram Transport Layer Security (DTLS) is considered to be one of the most suited protocols for securing the IoT. However, computation and communication overheads make it very expensive to implement DTLS on resource-constrained IoT sensor nodes. In this work, we profile the energy costs of DTLS 1.3, using experimental models for cryptographic computations and radio-frequency (RF) communications. Based on this analysis, we present eeDTLS, a low-energy variant of DTLS, that provides the same security strength as DTLS, but has lower energy requirements. By employing a combination of packet size reduction and optimized handshake computations, eeDTLS can provide up to 45% energy savings in a typical IoT use case. eeDTLS can be implemented in conjunction with any low-energy IoT RF protocol, and the proposed energy models and protocol optimizations can also be used to improve the energy efficiency of custom IoT security architectures.
Utsav Banerjee, Chiraag Juvekar, Samuel H. Fuller, Anantha P. Chandrakasan
GLOBECOM1