In this paper, the scheduling of yard cranes (YCs) and external trucks (ETs) working in a U-shaped automated container terminal yard is proposed as a new problem. This problem arises due to the characteristic of the U-shaped layout, where the ETs enter the yard through the U-shaped lanes and interact with the YCs. To formulate this problem, a three-objective optimization model is established to simultaneously schedule YCs and ETs, considering their efficiencies. Its solution is based on the nondominated sorting genetic algorithm III (NSGA-III), which is improved during initialization, crossover and mutation to make it applicable to the problem. To calculate the objective values in each iteration of the NSGA-III, a method to make the equipment interactions equal at all times is proposed. As there are special requirements for the priority of the objectives, a new method of selecting the final solution is presented, which leads to a more suitable solution. The case study involving sensitivity analysis shows that appropriate equipment quantity arrangement and task assignments have a positive impact on improving the efficiency of yard operations. Experimental results demonstrate that the proposed model and algorithms perform better. In summary, the model and algorithms proposed in this paper can effectively solve the proposed problem, which can offer a variety of options for decision-makers in an actual terminal operation environment.Note to Practitioners—The YC scheduling of a U-shaped layout presents new characteristics, and the influence of ETs cannot be ignored, posing a novel problem. Furthermore, during the operation of container terminals, extended waiting time for ETs is often caused by considerations related to ship schedules, especially in the mixed stacking mode. This can frustrate cargo owners and waste valuable ET resources. Hence, this paper designs a joint scheduling strategy for YCs and ETs in U-shaped yard layouts. The proposed strategy combines optimizing YC operation plans with maximizing ET efficiency, while ensuring efficient yard operations.

Matrix computation units have been equipped in current architectures to accelerate AI and high performance computing applications. The matrix multiplication and vector outer product are two basic instruction types. The latter one is lighter since the inputs are vectors. Thus it provides more opportunities to develop flexible algorithms for problems other than dense linear algebra computing and more possibilities to optimize the implementation.

Fast Fourier transform (FFT) is widely used in scientific and engineering computation. Recently developed matrix computation units for AI and high-performance computing provide new optimization opportunities for the FFT algorithm. Compared to dedicated matrix multiplication architectures like Intel AMXs, ARM’s Scalable Matrix Extension (SME) provides more flexible outer product instructions to construct matrix multiplications in software. To leverage ARM SME’s matrix multiplication capabilities, this paper proposes a novel optimized outer product pattern for the Cooley-Tukey FFT algorithm and presents OpenFFT-SME, the first FFT library for ARM SME based on this pattern. This pattern can reduce the number of outer product operations and memory accesses to the DFT matrix by exploiting the symmetric and periodic properties of twiddle factors in the DFT matrix. To further boost performance, OpenFFT-SME incorporates software pipelining to enhance execution pipelines in the assembly code kernels. Meanwhile, a butterfly network more suitable for this pattern is designed and integrated. Experiments demonstrate that OpenFFT-SME outperforms vectorization methods on ARM SME CPUs, achieving 3.60x (power of two) and 4.14x speedups (non-power of two) in double-precision compared to FFTW, 2.47x (power of two) and 3.21x (non-power of two) speedups in double-precision compared to FFTE, and speedups of 4.38x (power of two) and 7.02x (non-power of two) in single-precision compared to FFTW. Furthermore, we compare the advantages and disadvantages of our implementation against vectorization methods and analyze its performance characteristics through additional experiments.

Benefits from the simplicity, fastness and accuracy, the LogP model family is widely used to predict the parallel application communication performance, especial for the large-scale parallel application prediction or online prediction. However, this type of methods usually lacks consideration of modeling the network contention effect. This hinders their performance in predicting some real-world parallel applications. We thus propose a new parallel computation model via extending the LogGOPS mode with a parameter C. The additional parameter C is the additional time overhead caused by the network contention and it is predicted by a designed BP neural network. The experimental results show that LogGOPSC is more accurate than LogGOPS when there occur network contentions. Compared to the LogGOPS model, LogGOPSC gains a 93.25% average accuracy improvement for predicting 8mb point-to-point message passing. Furthermore, the average error of predicting two communication patterns is as low as 14.50% on the TianHe-2 HPC system.