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Sameer Arora

dblp:215/0383 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2024
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Program verification · 61% Compilers and program optimization · 30% Program analysis · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization › compiler optimization
memory partitioning
0.812024
Practical Verification of Smart Contracts using Memory Splitting · Proc. ACM Program. Lang. 2024
Program verification › code-level verification
smart contract verification
0.812024
Practical Verification of Smart Contracts using Memory Splitting · Proc. ACM Program. Lang. 2024
Program verification
SMT-based verification
0.812024
Practical Verification of Smart Contracts using Memory Splitting · Proc. ACM Program. Lang. 2024
Program analysis › static analysis
pointer analysis
0.212024
Practical Verification of Smart Contracts using Memory Splitting · Proc. ACM Program. Lang. 2024

Methods — techniques the papers use, named apart from their topics

pointer analysis · 0.8memory allocation recovery · 0.8SMT solving · 0.8
YearPublicationVenuePosition
2024 Practical Verification of Smart Contracts using Memory Splitting
abstract
SMT-based verification of low-level code requires modeling and reasoning about memory operations. Prior work has shown that optimizing memory representations is beneficial for scaling verification—pointer analysis, for example can be used to split memory into disjoint regions leading to faster SMT solving. However, these techniques are mostly designed for C and C++ programs with explicit operations for memory allocation which are not present in all languages. For instance, on the Ethereum virtual machine, memory is simply a monolithic array of bytes which can be freely accessed by Ethereum bytecode, and there is no allocation primitive. In this paper, we present a memory splitting transformation guided by a conservative memory analysis for Ethereum bytecode generated by the Solidity compiler. The analysis consists of two phases: recovering memory allocation and memory regions, followed by a pointer analysis. The goal of the analysis is to enable memory splitting which in turn speeds up verification. We have implemented both the analysis and the memory splitting transformation as part of a verification tool, CertoraProver, and show that the transformation speeds up SMT solving by up to 120× and additionally mitigates 16 timeouts when used on 229 real-world smart contract verification tasks.
Shelly Grossman, John Toman, Alexander Bakst, Sameer Arora, Shmuel Sagiv, Chandrakana Nandi
Proc. ACM Program. Lang.4
2016 Effect of sampling time and sampling instant on the frequency response of a boost converter
abstract
DC-DC converters like boost, buck-boost and flyback converters have unstable internal dynamics and are classified as non-minimum phase systems. The linear approximation of these DC-DC converters around the equilibrium point shows a zero that maps to the open right-half plane (RHP) of the complex s-plane. This paper models the boost converter using State Space Averaging (SSA) and Enhanced State Space Averaging (ESSA) to show changes in bode response as function of sampling time. Further, we use Discrete Modeling Analysis (DMA) to model the changes in transfer function with change in sampling instant when sampled during off-time of the switch. The result shows that significant bandwidth improvement can be achieved when sampling instant is rightly chosen during the off-time. Such a choice is easily achieved with a digital implementation for a DC-DC converter.
Sameer Arora, Poras T. Balsara, Dinesh K. Bhatia
IECON1