Recent advances in reasoning-capable large lan-guage models (LLMs) have led to their application in a wide range of tasks, including log parsing. These LLMs generate intermediate reasoning traces during inference, offering a unique opportunity to analyze and improve their performance. In this work, we investigate how reasoning traces can be leveraged to enhance LLM-based log parsers. We propose TraceDoctor, a framework that analyzes reasoning traces associated with parsing errors to understand the causes of failure. We categorize these error causes into high-level error types and design targeted log variant generation strategies guided by these high-level error types. The generated variants are then used to fine-tune the LLMs. We instantiate five state-of-the-art (SOTA) reasoning-capable LLMs as log parsers and identify 29 distinct high-level error types. Our approach improves their average parsing accuracy by up to 17.3% and 16.3% on parsing accuracy (PA) and group accuracy (GA), respectively.

APT attacks are becoming increasingly complex and stealthy. To effectively counter APT attacks, modelling threat intelligence data based on graphs, identifying Indicators of Compromise (IOC) nodes, and providing early warnings have become new research hotspots. However, the problem of node category imbalance in such graph datasets restricts the identification capabilities of these methods. Therefore, this paper proposes a supervised graph data augmentation method. In the training phase, graph disentangled representation learning is utilized to perform feature embedding for minority class nodes, effectively alleviating the sparsity problem faced by traditional methods and effectively integrating neighbourhood information of minority class nodes at a higher semantic level. Additionally, two loss functions designed based on link prediction and prototype constraints enhance node type consistency and semantic consistency, respectively. Experimental results on the APT and PDNS datasets demonstrate that the proposed method outperforms other baseline models in identification performance; even in highly imbalanced scenarios, it surpasses the second-best model.

Full-bridge power-factor-correction (PFC) front-end + dual-active-bridge (DAB) AC/DC topology is widely used in industry, e.g., electrical vehicle on-board charger. Such two-stage topology limits the system efficiency, and the bulky DC link bus capacitor makes the system power density relatively low. Compared to the two-stage design, the single-stage design, unfolding bridge + DAB, eliminates the bulky DC link bus capacitor and operates the front-end with only 60Hz switching frequency, thereby has the potential to increase the system power density and efficiency. A novel variable-switching-frequency and hybrid single-dual-phase-shift (VSF-SDPS) control strategy is proposed and analyzed for the DAB based single-stage topology. The proposed VSF-SDPF control consists of two phase shifts to guarantee Zero-Voltage-Switching (ZVS) over the full range of the AC line voltage, and frequency modulation to achieve boost PFC. The conventional front-end PFC is simplified to an unfolding bridge by changing DAB control strategy to achieve PFC and ZVS at the same time. Besides, a special ZVS boundary is utilized to solve the grid current distortion problem when the switching frequency saturated, which is especially severe at light load condition. Simulation results and experimental validation are presented under 50Vrms AC line voltage and 200V DC battery voltage test condition.