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Kartheek Rangineni

dblp:215/3451 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 61% Integrated circuit design · 30% Hardware reliability and fault tolerance · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN accelerator
energy-efficient DNN accelerator		 0.312018
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators · DAC 2018
Hardware accelerators and domain-specific architectures
machine learning accelerator		 0.312018
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators · DAC 2018
Integrated circuit design › low-power circuit design
voltage underscaling		 0.312018
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators · DAC 2018
Hardware reliability and fault tolerance
timing error tolerance		 0.112018
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators · DAC 2018

Methods — techniques the papers use, named apart from their topics

run-time DNN pruning · 0.3post-synthesis timing simulation · 0.3
YearPublicationVenuePosition
2018 Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators
abstract
Hardware accelerators are being increasingly deployed to boost the performance and energy efficiency of deep neural network (DNN) inference. In this paper we propose Thundervolt, a new framework that enables aggressive voltage underscaling of high-performance DNN accelerators without compromising classification accuracy even in the presence of high timing error rates. Using post-synthesis timing simulations of a DNN accelerator modeled on the Google TPU, we show that Thundervolt enables between 34%-57% energy savings on state-of-the-art speech and image recognition benchmarks with less than 1% loss in classification accuracy and no performance loss. Further, we show that Thundervolt is synergistic with and can further increase the energy efficiency of commonly used run-time DNN pruning techniques like Zero-Skip.
Jeff Zhang 0001, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg
 DAC2