Arnab Bag

dblp:215/3479 · DBLP profile ↗
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10ranked-venue papers
6as first author
7since 2021 · last 2024
0000-0003-1182-493XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 6 · 3 first-author · 4 since 2021Systems, architecture and hardware · 4 · 3 first-author · 3 since 2021
YearPublicationVenuePosition
2024 Tokenised Multi-client Provisioning for Dynamic Searchable Encryption with Forward and Backward Privacy
abstract
Searchable Symmetric Encryption (SSE) has opened up an attractive avenue for privacy-preserved processing of outsourced data on the untrusted cloud infrastructure. SSE aims to support efficient Boolean query processing with optimal storage and search overhead over large real databases. However, current constructions in the literature lack the support for multi-client search and dynamic updates to the encrypted databases, which are essential requirements for the widespread deployment of SSE on real cloud infrastructures. Trivially extending a state-of-the-art single client dynamic construction, such as ODXT (Patranabis et al., NDSS'21), incurs significant leakage that renders such extension insecure in practice. Currently, no SSE construction in the literature offers efficient multi-client query processing and search with dynamic updates over large real databases while maintaining a benign leakage profile.
Arnab Bag, Sikhar Patranabis, Debdeep Mukhopadhyay
AsiaCCS1
2023 Learn from Your Faults: Leakage Assessment in Fault Attacks Using Deep Learning
Sayandeep Saha, Manaar Alam, Arnab Bag, Debdeep Mukhopadhyay, Pallab Dasgupta
J. Cryptol.3
2023 TWo-IN-one-SSE: Fast, Scalable and Storage-Efficient Searchable Symmetric Encryption for Conjunctive and Disjunctive Boolean Queries
abstract
Searchable Symmetric Encryption (SSE) supports efficient yet secure query processing over outsourced symmetrically encrypted databases without the need for decryption. A longstanding open question has been the following: can we design a fast, scalable, linear storage and low-leakage SSE scheme that efficiently supports arbitrary Boolean queries over encrypted databases? In this paper, we present the design, analysis and prototype implementation of the first SSE scheme that efficiently supports conjunctive, disjunctive and more general Boolean queries (in both the conjunctive and disjunctive normal forms) while scaling smoothly to extremely large encrypted databases, and while incurring linear storage overheads and supporting extremely fast query processing in practice. We quantify the leakage of our proposal via a rigorous cryptographic analysis and argue that it achieves security against a well-known class of leakage-abuse and volume analysis attacks. Finally, we demonstrate the storage-efficiency and scalability of our proposed scheme by presenting experimental results of a prototype implementation of our scheme over large real-world databases.
Arnab Bag, Debadrita Talapatra, Ayushi Rastogi, Sikhar Patranabis, Debdeep Mukhopadhyay
Proc. Priv. Enhancing Technol.1
2023 CAMiSE: Content Addressable Memory-Integrated Searchable Encryption
abstract
Searchable symmetric encryption (SSE) is a special class of encryption schemes for computing directly over encrypted data. SSE aims to be significantly more efficient as compared to other solutions, such as fully homomorphic encryption (FHE), while leaking only minimal information to the adversary. SSE is particularly efficient and scalable for Boolean queries over large encrypted relational databases outsourced to third-party cloud service providers. However, practical implementations of SSE often suffer from performance bottlenecks due to randomised memory accesses for reads/writes and computation-intensive cryptographic operations. As a result, a gap exists today between theoretically efficient SSE algorithms and practically efficient SSE systems for real-world databases. In this paper, we address this longstanding open question that has otherwise hindered the widespread deployment of SSE over real cloud computing platforms. We proposeCAMiSE–a fully associative memory-integrated framework for designing SSE systems with fast query processing over extremely large databases. We show a novel usage of custom-designed Content Addressable Memory (CAM), together with robust data access policies, to bridge the memory wall in traditional SSE implementations by minimising storage-access latencies due to randomised look-up operations during searches. Coupled with dedicated hardware accelerators for cryptographic operations,CAMiSEachieves extremely fast and scalable query processing over encrypted relational databases. We prototype multiple well-known SSE algorithms and SSE data structures within our proposedCAMiSEframework. Our experiments show that these implementations achieve around$5\times $to$7\times $speed-up over traditional software-based implementations while scaling smoothly to extensive real-world databases with millions of records.
Arnab Bag, Sikhar Patranabis, Debdeep Mukhopadhyay
IEEE Trans. Circuits Syst. I Regul. Pap.1
2022 Work-in-Progress: CAMiSE: Content Addressable Memory-integrated Searchable Encryption
abstract
Searchable symmetric encryption (SSE) aims to support efficient query-execution directly over encrypted databases. Practical implementations of SSE suffer from performance bottlenecks due to randomised memory accesses and computation-intensive cryptographic operations. We propose CAMISE – a fully associative memory-integrated framework for designing SSE systems with fast query processing over large databases. We show a novel usage of custom-designed Content Addressable Memory (CAM) to minimise storage-access latencies during query execution in SSE systems. We prototype a well-known SSE scheme, namely Oblivious Cross Tags (OXT), within this framework. Our implementation achieves 5x-7x speed-up over traditional software-based implementations while scaling smoothly to real-world databases with millions of records.
Arnab Bag, Sikhar Patranabis, Debdeep Mukhopadhyay
CASES1
2022 FlexiPair: An Automated Programmable Framework for Pairing Cryptosystems
abstract
Pairing cryptosystems are extremely powerful mathematical tools for developing cryptographic protocols that can provide end-to-end security for applications like Internet-of-Things (IoT), cloud services and cyber-physical systems (CPS). However, these applications require the implementations to be light-weight but still real-time, with the additional feature of being flexible. The flexibility can come from different choices of underlying algorithms along with suitable parameter choices. A software implementation offers better flexibility but lacks in timing performance, whereas custom hardware delivers better performance but has poor flexibility. Furthermore, the designs over small characteristic curves are now insecure against recent attacks. Existing designs do not address the drawback of less flexibility and huge resource consumption collectively. In this article, we present a micro-program controlled hardware design which has the least resource consumption among the similar existing designs on FPGA that offer such programmability and flexibility. This redundant number arithmetic-based architecture consumes only 2506 slices on Xilinx Virtex-7 FPGA. It can be migrated to other device families or updated for different algorithms without data-path or control-path modification. To enhance the flexibility, we developed a custom assembly-like finite state machine (FSM) description, called Prism, and necessary tool to generate the micro-program states. To illustrate the functionality of Prism, we present designs for Tate and Optimal-Ate pairing with the micro-program states generated using this tool.
Arnab Bag, Debapriya Basu Roy, Sikhar Patranabis, Debdeep Mukhopadhyay
IEEE Trans. Computers1
2021 Divided We Stand, United We Fall: Security Analysis of Some SCA+SIFA Countermeasures Against SCA-Enhanced Fault Template Attacks
Sayandeep Saha, Arnab Bag, Dirmanto Jap, Debdeep Mukhopadhyay, Shivam Bhasin
ASIACRYPT (2)2
2020 Fault Template Attacks on Block Ciphers Exploiting Fault Propagation
Sayandeep Saha, Arnab Bag, Debapriya Basu Roy, Sikhar Patranabis, Debdeep Mukhopadhyay
EUROCRYPT (1)2
2020 Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks
abstract
Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some form of redundant computation to detect and react/correct the injected faults. However, such countermeasures are shown to be vulnerable to selective fault injections. In this article, we aim to develop a cryptographic primitive that is fault tolerant by its construction and does not require to compute the same value multiple times. We utilize the effectiveness of Neural Networks (NNs), which show “some degree” of robustness by functioning correctly even after the occurrence of faults in any of its parameters. We also propose a novel strategy that enhances the fault tolerance of the implementation to “high degree” (close to 100%) by incorporating selective constraints in the NN parameters during the training phase. We evaluated the performance of revised NN considering both software and FPGA implementations for standard cryptographic primitives like 8×8 AES SBox and 4×4 PRESENT SBox. The results show that the fault tolerance of such implementations can be significantly increased with the proposed methodology. Such NN-based cryptographic primitives will provide inherent resistance against fault injections without requiring any redundancy countermeasures.
Manaar Alam, Arnab Bag, Debapriya Basu Roy, Dirmanto Jap, Jakub Breier, Shivam Bhasin, Debdeep Mukhopadhyay
ACM J. Emerg. Technol. Comput. Syst.2
2018 Hardware Acceleration of Searchable Encryption
abstract
Searchable symmetric encryption (SSE) allows a client to outsource the storage of her data to an (untrusted) server in a private manner, while maintaining the ability to selectively search over it. A key feature of all existing SSE schemes is the tradeoff between security (in terms of the information leakage to the server) and efficiency (in terms of the operational and storage overhead on the server and client sides). The premise of this work is that SSE schemes typically offer scope for massively parallel implementations with improved efficiency without compromising security. Based on this idea, we propose a highly scalable framework for parallelized SSE implementations using hardware-based crypto-accelerators, interfaced with a software-based control unit and a memory controller unit. We choose field programmable gate arrays (FPGAs) as the platform for the crypto-accelerators due to their flexibility, reconfigurability, low time-to-market and low maintenance overheads. As a case study, we illustrate how the recently proposed SSE scheme of Lai et al. (CCS'18) may be implemented as per our framework, and the benefits thereof, including shorter preprocessing time and reduced query-response latency as compared to a software implementation.
Arnab Bag, Sikhar Patranabis, L. Tribhuvan, Debdeep Mukhopadhyay
CCS1