This paper proposes Virtual Fitting Room (VFR), a novel video generative model that produces arbitrarily long virtual try-on videos. Our VFR models long video generation tasks as an auto-regressive, segment-by-segment generation process, eliminating the need for resource-intensive generation and lengthy video data, while providing the flexibility to generate videos of arbitrary length. The key challenges of this task are twofold: ensuring local smoothness between adjacent segments and maintaining global temporal consistency across different segments. To address these challenges, we propose our VFR framework, which ensures smoothness through a prefix video condition and enforces consistency with the anchor video — a 360°-view video that comprehensively captures the human's whole-body appearance. Our VFR generates minute-scale virtual try-on videos with both local smoothness and global temporal consistency under various motions, making it a pioneering work in long virtual try-on video generation. Project Page: https://immortalco.github.io/VirtualFittingRoom/.

This paper introduces a 0.5-V, two-stage, pseudo-differential bulk-driven operational transconductance amplifier with high gain and linearity for low-power continuous-time applications. The input stage’s common-mode feedback utilizes a linear resistor detector with a conductance reduction cross-coupled pair to mitigate the loading effect of the common-mode detector resistor at ultra-low power operations. Temperature dependence of the conductance reduction circuit is compensated. The impact of the conductance reduction circuit on linearity performance is explored. The output stage employs a class-AB topology and utilizes a phase lead compensator to stabilize the OTA. Implemented in 180 nm CMOS technology, this OTA achieves a DC gain and slew rate of 68 dB and 26.1 V/$\mu $s, respectively, under a capacitive load of 10 pF. The total power consumption is$34.2~\mu $W. With unit gain feedback configuration, the measured total harmonic distortion is only 0.02% at an output amplitude of 500 mVpp. Test results validate the proposed circuit, positioning it competitively compared to state-of-the-art designs.

This paper presents a reconfigurable 4.75-to-32 GBuad transmitter (TX) that operates up to 64Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 32Gb/s with non-return-to-zero (NRZ) modulation scheme, designed in the 28-nm CMOS technology. The TX incorporates a quarter-rate architecture with a tap coefficient flexible feed-forward equalizer (FFE) up to 3 FFE taps. The TX employs a tailless CML driver with common-mode feedback (CMFB) for output swing control which provides 0.8 V pp output swing, and a helical wiring T -coil for bandwidth expansion. The clock path of the TX includes the duty-cycle detection/correction (DCD/DCC) circuits with a resolution of sub-60fs and quadrature-error detection/correction (QED/QEC) circuits, and a LC phase locked loop (PLL) with a local injection-locked (IL) quadrature clock generation circuit. The TX operating at 64 Gb/s in PAM-4 modulation consumes 76.7 mW from 1-V supply with 0.8 V pp, achieving an 1.2 pJ/b energy efficiency. The TX front end occupies an active area of 0.063 mm2.