This paper presents a 915 MHz ultra-low-power (ULP) receiver based on a single-path third-harmonic mixing (SPTHM) architecture. Unlike conventional multi-path sub-harmonic receivers that require precise multi-phase local oscillators (LOs), this work simplifies the receiver to a single-mixer path architecture by jointly optimizing the LO harmonic order and duty cycle. The receiver is driven by a 10%-duty-cycle LO operating at one-third of the carrier frequency ($f_{\mathrm {c}}$). Compared to the typical 50%-duty-cycle LO in the SPTHM configuration, the proposed receiver improves the conversion gain by 12.1 dB and noise figure (NF) by 5.2 dB. The architecture also exhibits a front-end NF variation of less than 1 dB across the 3%-13% LO duty-cycle range, thereby relaxing constraints on pulse generation. To facilitate ULP channel selection, a comparison-skipped frequency-locked loop (FLL) is used, consuming just$5~\mu $W. A high-Q IF amplifier with an improved active inductor load is incorporated to enhance in-band interference rejection, achieving 31 dB signal-to-interference ratio (SIR) at 5 MHz offset. Fabricated in a 65 nm CMOS, the receiver achieves a sensitivity of −86 dBm at 250 kbps data rate with a$39.4~\mu $W power consumption, including an on-chip LO. It indicates a competitive figure-of-merit (FoM) of 184 dB within a compact active area of 0.16 mm2.

This paper presents an energy-efficient spike-sorting system-on-chip (SoC) designed for closed-loop brain-computer interfaces of massive probing channels. The design first incorporates a sparsity/similarity-aware spike detection scratchpad, leveraging a bit-wise differential encoder and zero-friendly read-out circuits, reducing the dynamic power consumption of spike detection by 77.7%. To mitigate static power dissipation, it also introduces an ultra-low-leakage dual-voltage 5T-SRAM array with level-shifter embedded sense amplifiers, achieving an 82.2% leakage power reduction of neural signal buffering by applying half$V_{DD}$on SRAM cells. Additionally, a memory hierarchy architecture combining on-chip SRAM and off-chip FeRAM, along with a firing-rate-based Osort for cluster template management, minimizes off-chip memory access to only 9.7% with a latency of$11.7\mu $s for 1024-channel spike sorting. A silicon prototype is fabricated in 28-nm CMOS technology, which achieves a power consumption of 583nW/channel and an area consumption of 0.0012mm2/channel. The chip supports real-time spike sorting with up to 16K templates,$21.3\times $greater than the state-of-the-art spike-sorting processor.

This paper presents a 915MHz multi-channel receiver for ultra-low-power (ULP) applications. A sub-passive third-harmonic mixer is proposed to improve the front-end conversion performance at the ULP budget. Driven by the local oscillator (LO) that operates at one-third of the RF carrier frequency with a duty cycle of about 10%, the proposed mixer improves the front-end’s noise figure (NF) to 15dB while reducing the LO power consumption by three times. The mixer also alleviates the requirement for LO phase accuracy. With the LO duty cycle ranging from 4% to 14%, the variation of the mixer performance is less than 10%, which allows a simple pulse generation approach without a precise duty cycle control circuit, thereby saving power consumption. A low-power frequency-locked loop (FLL) with a 196kHz tuning step facilitates channel selection. Additionally, a high-Q intermediate-frequency (IF) amplifier with an active inductor is used to suppress in-band interference and noise bandwidth. Implemented in a 65nm CMOS process and based on post-simulation results, the receiver achieves a sensitivity of −88dBm while consuming 40µW at a 250kb/s data rate. The receiver also performs an improved figure-of-merit (FoM) of 186dB with 26dB interference tolerance and a compact active area of 0.16mm2.

This paper presents a 915MHz bit-level duty-cycled (BLDC) wake-up receiver (WuRX) designed for ultra-low-power Internet-of-Things (IoT) systems. Utilizing an envelope-tracking (ET) mixer, the WuRX generates a phase-following (PF) local oscillator (LO) from the incoming radio-frequency (RF) signals. The recovered PF LO has a low duty cycle of about 10% and aligns the peak and valley voltages of the RF signal. As a result, the on-off keying data is accurately downconverted to the baseband with improved gain. Moreover, the high-speed sampling capability of the ET mixer allows the receiver’s front-end to operate at a low duty cycle of 0.024%, significantly lower than other mixer-based BLDC WuRXs. Dynamic baseband amplifiers with pre-charging and auto-zeroing abilities are employed to save area and reduce power consumption. Fabricated in a 65nm CMOS process, the proposed BLDC WuRX achieves a sensitivity of −73.2dBm at a 1kbps data rate, consuming only 97nW and occupying an ultra-low-area of 0.036mm2.

This paper presents an ultra-low-voltage (ULV) and ultra-low-power (ULP) voltage detector (VD) for energy harvesting systems (EHS). The VD is designed using a 2-transistor (2T) voltage detection circuit and a 2T bias circuit. By leveraging two types of transistors with small threshold voltage differences, the detection voltage is reduced to 240 mV, enhancing the feasibility and practicality of the design for ULV EHS. The detection voltage can be programmed by incorporating an appropriate voltage divider into the VD, while the proposed 2T bias technique reduces its variation across different process corners. The design is implemented in a 65 nm CMOS process and occupies a chip area of 260 µm2. Post-layout simulation results indicate that the VD achieves a detection voltage of 240 mV, with a standard deviation (σ) of 6.6 mV, drawing only 5 nA of current at a supply voltage of 0.3 V. The average temperature coefficient (TC) across five process corners is 33.8 µV/°C, simulated within a temperature range of -40 °C to 125 °C.

The closed-loop deep brain stimulation system demands high-performance seizure detection, especially in terms of ultra-low power consumption and patient specificity. In this paper, we propose a seizure detection approach featuring low-pass filters for feature extraction and a programmable linear support vector machine for classification. This approach effectively reduces power consumption while retaining the signal energy near the cutoff frequencies and preserving the correlation between adjacent frequency bands. To reduce the false alarm rate, a Hidden Markov Model is utilized for post-processing. The proposed processor also employed calculation bit-width optimization and time-division multiplexing to minimize power and area consumption, while maintaining minimal accuracy loss. Implemented in a 65-nm CMOS process, the processor occupies an active area of 0.14 mm2. It achieves an energy classification efficiency of 0.473 μJ/class with 0.7-V supply and 16.384-kHz system clock. The measurement results show a sensitivity of 95.92%, a specificity of 98.11%, and a false alarm rate of 1.78 times/h, as validated by the CHB-MIT dataset.

A reference double-sampling phase-locked-loop-based (RDSPLL-based) multi-phase clock generator (MPCG) for DDR PHY is presented. The reference double-sampling architecture is utilized to achieve low phase noise. A CDAC-embedded voltage offset calibration is proposed to reduce jitter and reference spur, and a CMP-ADC hybrid phase detector is adopted to accelerate the locking process. Fabricated in 65nm, the proposed MPCG achieves better than 1° phase accuracy with a 100MHz reference clock. The reference spur is reduced from -56dBc to -80dBc and the locking time is reduced from 10.5us to 1.6us. The measured RMS jitter is 674fs at 2.4GHz with 3.43mW, yielding the FOMJitter-Nof -251.9dB.

This paper presents a reference double-sampling phase-locked loop (RDSPLL) that integrates frequency multiplication and octa-phase clock generation into a single system, significantly reducing power consumption. A differential ring oscillator (DRO) is employed to generate octa-phase clocks with high phase accuracy. The reference double-sampling technique extends the loop bandwidth, effectively suppressing phase noise from the ring oscillator and thereby reducing jitter. To achieve accurate and efficient phase error detection, we proposed a novel offset-compensated hybrid phase detector (OCH-PD), featuring an offset calibration and a comparator-ADC hybrid quantizer. The offset calibration utilizes the CDAC to dynamically compensate for the mismatch in double-sampling, improving jitter and spur performance. The hybrid quantizer supports dynamic mode switching based on different locking states: during the coarse frequency locking phase, it operates in the ADC mode to accelerate the locking process; once a stable lock is achieved, it switches to the comparator mode to enable low-power, high-speed quantization. Fabricated in a 65-nm CMOS process, the prototype achieves 674 fs RMS jitter at 2.4 GHz while consuming only 3.43 mW, resulting in a$\text {FOM}_{\text {Jitter-N}}$of -251.9 dB. With offset calibration, the reference spur at 100 MHz is suppressed from -56 dBc to -80 dBc, and the jitter is reduced from 1.42 ps to 674 fs. The locking time improves from$10.5~{\mu }$s to$1.6~{\mu }$s using the hybrid quantizer. The eight-phase accuracy remains better than 1° over the frequency range of 2-2.8 GHz.

Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of$\mathbf{2.53} \mu \mathbf{W}/\mathbf{channel}$and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

This work proposes a high-speed pipelined-two-step time-to-digital converter (TDC) with a dynamic time amplification (DTA) to improve the resolution at low power. The key element of this TDC is the DTA. It samples the residual time errors as voltages held in the MOM capacitors and discharges them to generate the amplified time difference. Thanks to the dynamic time-voltage-time conversion, the DTA realizes high linearity and power efficiency, and can be employed to build a pipeline TDC architecture with high sampling frequency because of its sample and hold operation. Moreover, the DTA maintains constant gain, so only a one-time forground calibration for gain mismatch is required in this TDC. Simulations show that the TDC designed in 65 nm CMOS achieves 8-bit, 1.75 ps of time resolution, and 1 LSB INL and 1.6 LSB DNL with one-time foreground calibration at 400 MHz sampling frequency while just consuming 726 μW power, which corresponds to 18.45 fJ/Conv. FoM.

A low-voltage low-power 16-channel neural interface front-end IC for in-vivo neural recording applications is presented in this paper. A current reuse telescope amplifier is used to achieve better noise efficiency factor (NEF). Power efficiency factor (PEF) is further improved by reducing supply voltage with the proposed level-shifted feedback (LSFB) technique. The neural interface is fabricated in a 65 nm CMOS process. It operates under 0.6V supply voltage consuming 1.07 μW/channel. An input referred noise of 5.18 μV is measured, leading to a NEF of 2.94 and a PEF of 5.19 over 10 kHz bandwidth.

This paper presents an 8-channel power-efficient neural recording analog front-end (AFE) with high power-supply rejection ratio (PSRR) and wide dynamic range. The ultra-low power is achieved by using a low supply voltage current-reusing input stage in the low noise amplifier (LNA). In order to improve the PSRR in low supply voltage amplifiers, we propose a replica biasing circuit to generate the biasing current, which is insensitive to the supply noise. Furthermore, the dynamic range is enlarged by utilizing an averaged local field potential (A-LFP) feedback loop. The prototype is fabricated in a 65nm CMOS process. Each channel of the AFE occupies 0.04mm2and only consumes 340nW from 0.35V/0.7V dual supply. The AFE provides a maximum gain of 54dB with 6.7μV input-referred noise integrating from 0.5Hz to 6.5 kHz. The proposed 0.35V input stage can tolerate a supply interferer up to 200mVpp, while maintaining a PSRR of 74dB.

This paper presents a -88 dBm sensitivity, 150Kbp/s OOK mixer-first nonlinear receiver in 65nm CMOS operating at the 2.46GHz ISM band. Since the LNA in the 1stIF band can be saturated by the strong in-band interferer, the shifted limiter (SL) is used to improve the interference resilience. Hence, by using an input power detection block, the 1stgain stage in the 1stIF band can alternatively turn on the LNA or the SL to improve the dynamic range. The in-band SIR at +/-1, 3 and 5MHz are measured to be -43/-11, -53/-54 and -53/-56dB respectively, while just consumes 380 to 610μW.