This paper presents a multipath wide-bandwidth magnetic current sensor based on Hall effect. To simultaneously achieve wide bandwidth, minimal ripple and small area, the system incorporates a non-spun filter-free main path with offset elimination through a continuous-time compact auxiliary path. The auxiliary path cancels the main path offset via feedforward, alleviating the need for area-consuming blocking capacitor or DC servo loop. Therefore, the chip occupies only 1.52 mm2. To suppress ripple in the auxiliary path induced by spinning current, a ping-pong switch-capacitor (PPSC) filter is proposed which mitigates ripple by sampling and averaging in the forward path, with the system achieving a residual ripple of$4.1~{\mu }$T. Compared with the state-of-the-art Hall sensor, it achieves$5{\times }$bandwidth improvement,$2{\times }$ripple reduction while occupying$5{\times }$less area.

Millimeter-wave (mmW) phase-locked loops (PLLs) typically favor a wide loop bandwidth for stronger suppression of the out-of-band phase noise from a voltage-controlled oscillator (VCO). Unfortunately, doing so lowers the degree of attenuation to the PLL reference spurs. This paper proposes a ripple compensation phase detector (RCPD) for extending PLL loop bandwidth and phase noise suppression without sacrificing reference spur performance. The RCPD inherently consists of a pair of PDs that generate respective ripple simultaneously, with each PD’s ripple current compensating the other, resulting in a glitch-free RCPD output. A calibrator is also introduced to reduce device mismatches. With the proposed techniques, the proposed mmW PLL was implemented using 22 nm bulk CMOS technology. The mmW PLL operates from 32.7 to 39.4 GHz, achieving an integrated jitter and reference spur of 88.5 fsrms (1 kHz to 100 MHz) and –76.2 dBc, respectively, with a figure-of-merit (FoM) of –247.5 dB.

In this paper, an RC relaxation oscillator exhibiting robust performance over an extended temperature and supply range is proposed. By incorporating a digitally-assisted calibration loop, the design eliminates the errors from switch on-resistance, comparator offset and propagation delay. Fabricated using a 180 nm bipolar-CMOS-DMOS (BCD) process technology, the oscillator operates at a frequency of 7MHz with the supply sensitivity of 870 ppm/V across a voltage range of 1.7 to 4.2 V. The evaluation of 40 untrimmed samples achieved an average temperature coefficient (TC) of 52 ppm/$^{\circ}$C from$-$40$^{\circ}$C to 165$^{\circ}$C, with the worst observed TC being 81 ppm/$^{\circ}$C. The aging test results indicate small deviations of 0.3% and 11% in the oscillation frequency and its TC, respectively. Furthermore, the direct power injection test confirms its reliability and robustness with a maximum error of oscillation frequency of 6.4%.

This paper proposes a MOSFET-only voltage reference using the standard 1.2-V MOSFET based on the 65nm CMOS technology, which achieves a power supply voltage operating range of 0.65 V to 2.5 V and the line regulation is 443μV/V. This work demonstrates the technique to achieve a low temperature coefficient and the function of offset voltage cancellation by ZTC-MOS, therefore, the effects of the offset voltage are eliminated. Monte Carlo simulation verifications were conducted based on the TSMC CMOS 65-nm process. Within the temperature range of -40 °C to 150 °C, the voltage reference is 507.4 mV and the temperature coefficient is 23.88ppm/°C in a 160-run Monte Carlo simulation. The overall power consumption is only 6.825 μW at 0.65 V supply under the TT corner and the temperature is set in the typical 27°C.

This paper introduces the utilization of a high-bandwidth rail-to-rail operational amplifier in switching converters, which opens the door to advancing switching converters towards higher switching frequencies. As the switching frequency increases, the signal within switching converters also rises, frequently surpassing the switching frequency itself. Consequently, a high-bandwidth amplifier becomes imperative. The proposed operational amplifier is fabricated using the 0.18-μm BCD process and integrated into the voltage-seconds balance circuit of a multi-mode four-switch buck-boost (FSBB) converter for validation purposes. Post-layout simulation results demonstrate that the amplifier achieves a bandwidth of 400 MHz with a quiescent current of 140 μA. Furthermore, the amplifier is applied in a high-frequency four-switch buck-boost converter to meet the demands of high switching frequencies. The input voltage for the four-switch buck-boost ranges from 150 V to 420 V, while the output voltage is maintained at 28 V. The excitation inductance value is only 5 μH. Simulation results demonstrate that the switching frequency can be enhanced to 2 MHz with the use of the high-bandwidth operational amplifier.

This paper presents a highly integrated MOSFET-only voltage reference with load driving capability realized in BCD 153 process, featuring a temperature coefficient of 1.6 ppm/°C from -40°C to 125°C, a high PSR of 127dB, low noise of 63 nV@1KHz for the voltage reference part, and a temperature coefficient of 1.35 ppm/°C from -40°C to 125°C, a PSR of 86dB and a load driving capability of 1 mA for the LDO part. Incorporating an ultra-low average temperature coefficient and load-bearing capability, the circuit under consideration also boasts a remarkably high power-supply rejection ratio. Furthermore, it exhibits commendable performance in terms of stability, noise characteristics, step response, and power consumption. The entire circuit utilizes only 21 MOS transistors, making it significantly compact compared to the conventional approach of combining a voltage reference module with an LDO module, thus resulting in substantial area savings. Besides, this circuit also maintains a stable static operating point across process variations, supporting straightforward migration to alternative processes with only minor adjustments.

This paper introduces a tri-loop capacitor-less low dropout regulator (CL-LDO) that achieves enhanced transient response and PSRR. In the primary loop, a Folded-Cascode operational amplifier is used as the error amplifier (EA) to achieve higher gain. The second loop adds feedback by detecting the output voltage and summing the results into the main loop. The third loop is current feedback loop (CFL), which can adaptively increase the power transistor gate current to achieve better transient response and lower power consumption. This CL-LDO is implemented using a BCD 0.18-μm process and operates at 1.8 V. It can efficiently convert the input voltage ranging from 0.7 V to 1.8 V into a stable output voltage of 0.6 V. Simulation results demonstrate that when the load current jumps from 100 mA to 200 mA (which is half the range of load current), an overshoot of 9 mV and an undershoot of 8 mV can be achieved. Additionally, this LDO can achieve a line regulation of 0.096 µV/mA and a PSRR (Power Supply Rejection Ratio) of 99 dB@10KHz. Moreover, the proposed LDO can handle a maximum load current of 200 mA effectively. Overall, the proposed CL-LDO design showcases improved transient response, PSRR, and line regulation, making it highly suitable for power-efficient System-on-Chip (SOC) applications.

This paper presents a RC relaxation oscillator with wide temperature range for automotive application. By using a digitally assisted calibration loop, the comparator offset and the loop delay are efficiently cancelled. With both reference voltage and current derived from the same ΔVBE-based bias circuit, the proposed design cancels leakage currents and makes the design insensitive to high-temperature. The oscillator was fabricated in a 180 nm BCD process, the oscillator operates at 7MHz and achieves a supply sensitivity of 870 ppm/V from 1.7 to 4.2 V at room temperature. Measurements on 40 samples without trimming show that it has an average temperature coefficient of 52 ppm/°C over a wide temperature range (-40°C to 165°C), with the worst case temperature coefficient of 65 ppm/°C.

An innovative artificial magnetic conductor (AMC)-backed quad-band antenna is proposed with gain enhancement, high out-of-band (OoB) rejection, forward radiation improvement, and backward radiation reduction for intelligent Internet of Vehicle (IIoV)-based sensing and communication. It includes a quad-band microstrip radiator and a tetracyclic nested AMC as a reflector. The radiator has a radiating pattern of slotted octagonal patch connected to a rectangular resonant loop, and a meshed defected ground structure (MDGS). The mechanism of resonant frequency generation is derived and analyzed. Then, an AMC reflector with four zero-phases in the reflection coefficient is designed and its equivalent circuit model is established. The AMC unit cell consists of four nested rings and two lumped capacitors. It generates four in-phase reflection bands, which are coincident with the four frequency bands of the radiator. The quad-band antenna gains are enhanced while its profile maintains low due to the in-phase reflection characteristics of the multi-band AMC reflector. To verify the design concept, a prototype with a total size of 95 mm × 101 mm × 21.2 mm is fabricated and measured. The measured 10-dB impedance bandwidths are 2.19-2.54 (14.8%), 3.06-5.25 (52.7%), 6.43-6.96 (7.9%), and 7.71-8.29 (7.3%) GHz, respectively. High OoB rejections between each band reduce electromagnetic interference to feed into radiofrequency circuits. The measured gains and radiation efficiencies range from 3.6 to 8 dBi and from 57.8% to 92%, respectively.

With the rapid development of the techniques of semiconductors, Internet of Everything (IoE), industry 4.0 and smart power are going to be realized, agile and accurate edge detection on pulse signals becomes essential for supporting versatile sensing applications targeting ubiquitous IoE monitoring. To ensure accurate pulse signal sensing at the edge with low power, a novel silicon-integrated mixer-enabled adaptive sensing platform is proposed. Based on the innovative chip architecture composed of the low-power ring voltage-controlled oscillator (VCO) and current-bleeding mixer on-chip, the wideband pulse signal would be mixed with the sinusoidal LO signal generated by VCO and detected by low-pass filtering and further digital processing. The frequency of the VCO can be configured flexibly by the FPGA to cover different pulse detection scenarios. Moreover, the VGA and the LPF are flexibly configurable to meet the link budget requirements and ensure accurate and adaptable detection covering various scenarios. Based on the systematic theoretical evaluation of the novel flexible sensing chip architecture, target pulse signals can be detected, exploring the capability of the efficient chip-based edge pulse detection system to be deployed for applications such as sustainable partial discharge detection for power electronics monitoring, ultrasound sensing, and so on.

A novel mixed-signal adaptable silicon-based coherent photoacoustic (PA) sensing system-on-chip (SoC) is proposed to detect various kinds of target signals robustly under high noise and strong interferences in compact chip-level, attaining precise in vivo sensing for physiological signs monitoring and enhanced bio-imaging. Based on the configurable coherent PA sensing SoC architecture supported by on-chip Gilbert cell-based multiplier, a digital processing module, and DACs, in-phase (I) and quadrature (Q) templates generated by digital module on-chip are configurable to be with a high correlation coefficient to the target PA signal, attaining detection and reconstruction of target signals in a coherent detection mode. The correlation between the received PA signal and the templates is implemented efficiently, assuring accurate tracking and precise reconstruction on the target PA signals at the chip level. Based on the integrated PA SoC fabricated by the TSMC 65-nm CMOS process, precise in vivo sensing and imaging can be assured at the edge. Further, as PA detection leverages optical and ultrasound sensing, in vivo imaging on in-depth vessels or other tissues can be attained. The mixed-signal PA SoC paves the way for sustainable health monitoring and owns immense potential for early disease diagnostics based on in vivo blood temperature sensing and vessel imaging.

A 12th-order active-RC bandpass filter (BPF) for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed BPF is composed of six cascaded Biquads and each Biquad is configured as a second-order bandpass stage and the switched resistor and capacitor arrays are used in the Biquad to enable the digital control of the passband center frequency and bandwidth. To achieve desired passband and behave with Chebyshev response, the capacitors in the six Biquads are designed with the same values and resistor values are tunable. The filter has been implemented in a 65 nm CMOS technology and achieved low ripple, low noise and low power consumption. Under 8-bit digital programmable, the center frequency is tunable from 0.98 MHz to 4.83 MHz and the bandwidth is tunable from 0.66 MHz to 5 MHz, and it measures a maximum in-band frequency response deviation of <0.6dB while consuming $\leq$12mW at a 1.2 V supply.

With the rapid development of the internet of things (IoT), industry 4.0, smart manufacturing, intelligent building techniques, robots are becoming more and more demanding for emerging new applications. For robots used in complex environments, precise sensing of its surroundings is essential to enable safe and robust operation. Comprehensive and cognitive perception capability is needed to recognize human subjects in a complex and dynamic environment to avoid the possible collisions. Moreover, comprehensive sensing is required to enable accurate simultaneous localization and mapping (SLAM) under scenarios with clutters and moving human subjects. To achieve the goal, a CMOS-integrated radarassisted robot sensing platform is proposed. By leveraging the phased-array radar techniques and time-phase processing techniques, high accuracy can be achieved for localization and recognition of human subjects. Fabricated in a 65-nm CMOS process, the chip-scale radar sensing platform is with compact size. A series of experiments have been carried out on verifying the capabilities of the radar platform for ranging and human recognition based on vital signs, exploring the potential for seamless human-robot interaction applications.

An ultra-lower power (ULP) MEMS-based FSK transmitter is implemented in 65 nm CMOS. The transmitter operates in ISM-915 MHz band using a binary FSK modulator employing the high-Q dual microelectromechanical system (MEMS) resonators. The transmitter using an adaptive fast switching binary FSK modulator generates FSK signals in 915 MHz band with -8.2 dBm output power, supporting up to 10 Mb/s data rate. The phase noise (PN) of the FSK modulator was measured for each of the two different operation frequencies, achieving -139.4dBc/Hz and -138.7dBc/Hz at a 1-MHz offset at 911.9 MHz and 923.1 MHz, respectively. At 10 Mb/s, the transmitter consumes 753 pW, which translates to energy-efficiency of 75.3 pJ/b.

For wearable biomedical devices, it is essential to detect target signals under high noise and strong interferences. Moreover, it is critical to realize the system with compact size and easy implementation. To address both goals, this paper presents a chip-based photoacoustic (PA) sensor called QuACL. By leveraging the adaptive coherent lock-in technique, the high sensitivity and specificity can be achieved for detecting target signals. In-phase and quadrature PA templates are specifically designed based on the profile of the target signal and are generated by the FPGA board and the DAC board. The received signal is correlated with the templates to capture, track, and recover the target PA signal. Fabricated in 65-nm CMOS technology, the chip-based sensor system occupies only 0.6 mm2area. The robustness and versatility of the QuACL sensor system are verified by the experiments on discerning and recovering weak PA signals accurately.

Flexible and wearable devices are emerging with the developing of the sensors and IoT (internet of the things). The power consumption and volume of such devices are dominant limitations for wearable feature in various applications. To meet the requirements, a photoacoustic receiver system-on-chip (SoC) is developed and fabricated with a novel correlation detection technique based on the early-and-late tracking. Through this method, output SNR of the receiver can be significantly improved. For this, a low power and high sensitivity analog front-end (AFE) with a noise shaping (NS) SAR ADC is implemented. As oversampling is necessary for the accurate delay of digital processing, noise shaping technique is implemented in the SAR ADC. Simulation results show that, the AFE achieves 70 dB dynamic range and 20 μV sensitivity for about 30 dB output SNR. The SAR ADC can obtain 71 dB SNDR under 50MSps sampling rate with the aid of the NS technique. Based on the analog circuits design, the digital part for the detecting technique is also implemented on chip. The whole power consumption is about 15 mW on the TSMC 65 nm CMOS process.

The paper presents a two-stage cascade push-pull power amplifier (PA) with floating-body transistors in 130 nm Silicon-On-Insulator (SOI) CMOS process for IEEE 802.11ac application. In the proposed design, on chip baluns, which can realize impedance matching, are used in driver stage amplifier input and power stage amplifier output matching networks. The proposed PA can achieve high gain, high output power and wide bandwidth at the same time with 0.819mm2chip area including pads. With 2.5 V supply voltage, the implemented PA achieves 20.31 dB power gain with 3 dB bandwidth range from 3.9 GHz to 6.19 GHz, 20.96 dBm output power at 1 dB compression point (OP-1dB) and 9.85% power added efficiency (PAE).

Integrated frequency modulated continuous wave (FMCW) radar on chip (RoC) shows huge potential on real-time, versatile, wireless monitoring of human health conditions with low power, high sensitivity and compact size. This paper presents a Ku-band FMCW RoC working at 15 GHz center frequency, which can realize accurate continuous health monitoring based on interferometry phase analysis algorithm. A digital-tunable mixed-signal-mode FMCW chirp synthesizer is designed to ensure the phase accuracy with high power efficiency. A saturated driver-amplifier and power-amplifier chain is used to suppress the chirp ripples, thus ensuring the accurate phase measurement. Fabricated in 65 nm CMOS technology, the prototype demonstrates 1 GHz chirp bandwidth with 1.2 V supply and 238 mW power consumption, which satisfies the low-power requirement for continuous-time healthcare monitoring applications. Experiments on detecting various kinds of micro physiological signals are carried out using the FMCW radar chip prototype based on the phase analysis algorithm. The radar and the phase analysis algorithm can be further integrated into an ASIC to realize higher performance on healthcare monitoring.

In this paper, a delay locked loop (DLL) based configurable multi-phase clock generator with wide operating range and high resolution is proposed. It is implemented by adopting array of configurable DLLs and is able to generate multi-phase frequencies with true-time-delay, which is essential in a wideband FMCW phased array system. Fabricated in a 40nm CMOS process, the proposed multi-phase clock generator achieves configurable phase delay with high resolution of 7ps under varies of reference frequency from 400MHz to 2.5 GHz. The clock generator consumes 20.9mW from a 1.1V supply.

The paper presents a wideband, low-power chirp synthesizer for Ku-band FMCW radars. The DDS-driven ADPLL chirp synthesizer generates chirps up to 2GHz bandwidth. A low-power DDS is employed to generate a stepped reference frequency for ADPLL to ensure the long term chirp linearity, while the ADPLL fulfill the ramp-interpolating linearization by generating a narrow band chirp within the step frequency. The entire chirp benefits from the phase domain modulation and mitigates ADPLL loop bandwidth variation to achieve high linearity and low power. A novel adaptive ramping control scheme is adopted to ensure the chirp rate is constant after combining the narrow band chirp segments. By this two-stage chirp generation, a 2-GHz chirp is achieved with low relative frequency RMS error. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.9GHz to 15.9GHz with configurable rate from 0.25 to 4GHz/ms, and consumes 53.8mW.