Resistive Random Access Memory (RRAM) is a promising low-power memory candidate because of a large R-ratio (RHRS/RLRS). Multi-level RRAM cells have been investigated to improve memory density and cost-per-bit. However, sensing multi-level becomes challenging due to the smaller R-ratios between stored digital values. This paper introduces a novel time-based sensing (TBS) scheme for enhancing the sensing speed and robustness for single-level cells (SLC) to multi-level cells (MLC). The proposed time-based sensing scheme converts the bit line (BL) current into a time delay using a novel current-to-time converter (CTC). The BL-current-dependent time delays are utilized to generate digital data. In addition, the proposed sensing scheme executes sensing without need for reference current or reference voltage. Comprehensive simulation in 40nm CMOS technology shows that the proposed TBS scheme achieves better linearity and higher read speed by precise cell current replication in CTC compared to the prior TBS schemes. As a result, the proposed TBS reduces sensing latency by 230%~340% compared to the prior TBS schemes. Furthermore, the proposed TBS improves the variation tolerance of read operation by 5%~33% at 1.1 V.

Implementing parallel computing inside memory units, compute-in-memory (CIM) has shown significant energy and latency reduction, which are suitable for neural network accelerators, especially for low-power edge devices. This brief presents a compact 2T-eDRAM CIM structure to support signed 4b/4b/6b input/weight/output precision multiply-accumulate (MAC) operation, exploring a near-zero-skipping (NZS) technique to improve energy efficiency further and reduce weight update time. The center weight first (CWF) update method is proposed to extend the overall weight retention time. Furthermore, the analog multiplication and accumulation nonlinear compensation techniques are employed to improve the accuracy and linear range. Fabricated in 65-nm CMOS technology, this chip achieves the weight bit storage density of 3.7 Mb/mm$^{2}$and SWaP figure of merit of 210 TOPS/W Mb/mm$^{2}$. The measured energy efficiency shows an average of 55.8 TOPS/W with the 4b/4b/6b input/weight/output precision at 1.2 V and 100 MHz.

Resistive Random Access Memory (RRAM) is a promising low-power memory candidate because of a large R-ratio (RHRS/RLRS). Multi-level RRAM cells have been investigated to improve memory density and cost-per-bit. However, sensing multi-level becomes challenging due to the smaller R-ratios between stored digital values. This paper introduces a novel time-based sensing (TBS) scheme for enhancing the robustness and speed of the read operation, supporting from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the current-to-time converter (CTC) converts the bit line (BL) current into a time delay based on the cell states. Different time delays from HRS and LRS values are compared to generate digital data. Unlike conventional current-based sense amplifiers (CSA) or voltage-based sense amplifiers (VSA), the proposed sensing scheme does not require a reference array or generator. Comprehensive simulation in 40nm CMOS technology shows enhanced linearity and higher read speed because of the precise replication of cell current to CTC. As a result, the proposed TBS achieves a sensing latency of < 2ns with an energy consumption of 61fJ/bit for read operations at 1.1 V and also supports MLC sensing through a single read operation.

This paper presents a highly integrated MOSFET-only voltage reference with load driving capability realized in BCD 153 process, featuring a temperature coefficient of 1.6 ppm/°C from -40°C to 125°C, a high PSR of 127dB, low noise of 63 nV@1KHz for the voltage reference part, and a temperature coefficient of 1.35 ppm/°C from -40°C to 125°C, a PSR of 86dB and a load driving capability of 1 mA for the LDO part. Incorporating an ultra-low average temperature coefficient and load-bearing capability, the circuit under consideration also boasts a remarkably high power-supply rejection ratio. Furthermore, it exhibits commendable performance in terms of stability, noise characteristics, step response, and power consumption. The entire circuit utilizes only 21 MOS transistors, making it significantly compact compared to the conventional approach of combining a voltage reference module with an LDO module, thus resulting in substantial area savings. Besides, this circuit also maintains a stable static operating point across process variations, supporting straightforward migration to alternative processes with only minor adjustments.

Abstract For spectral clustering algorithm, the quality of eigenvectors of graph affinity matrix is very important for the clustering result. So, how to obtain high‐quality eigenvectors is crucial. In this paper, the authors aim to propose some new measurement methods to evaluate each eigenvector of affinity matrix for spectral selection. Based on extended information entropy, three criteria, i.e. Spectral Distinguishability (SD), Spectral Distinguishability Validity (SDV) and pectral Distinguishability ‐Degree (SDD), are defined respectively. The compactness of clusters for each eigenvector is measured by SD; SDV is used to remove the inefficient eigenvectors for clustering; SDD is used to evaluate the contribution of eigenvectors to clustering and is exploited to build a selective spectral ensemble scheme. To indicate the merits of the authors’ algorithm, the authors consider varied artificial data and natural images, including Berkeley image segmentation data set as benchmark data set. The authors’ simulation results confirm the superior performance of the proposed method in developing spectral clustering compared to conventional clustering methods and recent eigenvectors‐selection‐based algorithms.

Resistive random access memory (RRAM) is a promising emerging nonvolatile memory (NVM) due to its large resistance ratio in different switching states. To improve memory density and reduce cost-per-bit, multi-level cell (MLC) RRAM stores multiple bits in a single cell, compared to a single-level cell (SLC). However, random mismatch, process variation, and resistance shift lead to reliability issues, degrade the probability of correct read, and increase the bit error rate (BER). This paper presents a time-based sensing scheme for robust read operation and extends to multi-level sensing for SLC and MLC RRAM arrays. Bit line (BL) voltage is converted into time delay by a voltage-to-time converter (VTC) and compared with the implicit timing reference generated by a delay line. By detecting different states in the time domain, the proposed time-mode sense amplifier (TSA) requires no analog reference voltage or current, which is used in the conventional voltage-mode sense amplifiers (VSA) or current-mode sense amplifiers (CSA). Power gating is employed to enable the time sampling only at the sensing points to suppress the short-circuit current. A charge sharing-induced error compensation (CSEC) circuit is used to eliminate the charge sharing-induced voltage drop and expand the sense margin by$1.56\times $. Monte Carlo simulations in 40nm technology show that the proposed TSA improves read reliability and reduces BER by 3–4 orders of magnitude compared to conventional VSA and CSA. The proposed time-based sensing scheme operates from 0.7-1.2 V supply and consumes 49 fJ/bit for read operation under a nominal 1.2 V supply.

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 - 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 - 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training.

Using on-chip slow-wave transmission line (SW-TL) has paved a new way towards millimeter-wave (mm-wave) to terahertz (THz) low power and high speed inter-/intra-chip communications. This work presents an on-chip SW-TL featured by periodic comb-shape grooves with capability to strongly localize electric-field. A gradient groove structure is proposed to serve as the mode converter and performs the mode transformation between the quasi-TEM wave and the slow-wave with low return loss. Due to field confinement, when two SW-TL are only 2.4 μm apart, more than 19 dB crosstalk suppression is observed compared with two conventional TL with the same metal spacing. A dual-channel 160 GHz frequency-shift keying (FSK) transceiver is designed in 65 nm CMOS technology. The preliminary results show that by exploiting SW-TL as the silicon channel, the receiver can recover error-free 4 Gb/s dual-channel data, whereas the eye diagram of the transceiver using traditional transmission line (TL) is fully distorted. The transceiver consumes 36 mW DC power from a 1.2 V power supply.