Probabilistic-bit (p-bit) systems are promising computational platforms due to their potential for high energy efficiency, particularly when implemented using stochastic elements like low energy-barrier nanomagnets that exploit inherent thermal stochasticity. However, these stochastic elements are susceptible to getting stuck to a given state or transitioning too slowly due to faults arising during fabrication, ageing or other operational issues. This paper examines the impact of such faults on p-bit systems using a subset of the MNIST handwritten dataset as a case study and shows degraded system functionality due to such faults. To address these challenges, we propose a methodology based on mutual information to evaluate the criticality of individual p-bits in a network for a given application, quantifying their influence on system accuracy. Using the proposed criticality score (CS), we identify the most impactful p-bits and employ them in guiding fault-tolerance strategies. Additionally, we introduce the design of testable p-bits to detect faults in critical p-bits, validated through SPICE simulations using 14nmHP-FinFET technology. To further enhance fault resilience, we propose isolatable and fault-tolerant p-bits that help tackle accuracy loss caused by stuck-at faults. While these designs incur area overhead due to additional transistors, we can use the criticality score to replace only the most essential p-bits with fault-tolerant p-bits, minimizing unnecessary overhead while achieving desired fault-tolerance levels. Thus, this work demonstrates a comprehensive framework to develop fault-tolerance capabilities in a p-bit system implemented using stochastic elements susceptible to stuck-at faults.

Traditional standard cell libraries employ a single-input switching (SIS) assumption for characterization. However, in real circuits, multiple inputs can switch simultaneously, resulting in a significant speed-up. This discrepancy can lead to circuit failures due to inaccurate early analysis, despite static timing analysis (STA) tools adopting conservative strategies. Consequently, multi-input switching (MIS) models have gained importance for timing libraries. For complex logic gates, however, the number of possible transitions that must be considered for characterization increases significantly, posing a substantial challenge in modeling MIS effects. We propose a novel approach to address this challenge by combining the power of satisfiability (SAT) solvers and machine learning (ML) techniques. First, we perform a logical analysis on the Boolean function of a given logic gate to identify input patterns that can lead to MIS-induced speed-up. This task is formulated as a SAT problem, and a SAT solver is utilized to extract all MIS-relevant transitions, thereby significantly reducing the characterization and modeling effort. Next, we leverage ML techniques to accurately capture the complex dependencies of MIS-induced speed-up under various circuit and environmental conditions. To streamline this process, we introduce an automated tool framework named LiMo (Library Model), which integrates a SAT solver, SPICE simulator, dataset optimization strategies, ML training/testing infrastructure, and multiprocessing capabilities to create MIS-aware timing libraries. The results on benchmark circuits reveal that ignoring MIS effects can result in relative root mean square errors (RRMSE) exceeding 40% in timing attributes. In contrast, LiMo-generated libraries achieve RRMSE errors below 7% compared to SPICE simulations, while delivering results$\sim 10,000 \times $faster, underscoring their suitability for incorporating MIS effects in STA for industrial designs.

Probabilistic computing is a promising computational paradigm that harnesses the inherent stochasticity of devices to tackle problems that can benefit from stochastic-driven search. A probabilistic bit (p-bit), the workhorse of probabilistic computing, is popularly implemented using energy-efficient low-barrier nanomagnets, highly-scaled transistors, and unstable memory elements. These implementations are prone to process- and environmental-induced variations and aging-induced non-idealities. These non-idealities can manifest as unwanted bias in a p-bit and its incoming signals, impacting the figures of merit of probabilistic computing. For the first time, this work systematically investigates this aspect of probabilistic computing. First, we investigate the behavior of a non-ideal p-bit using an analytical model proposed in this work and corroborate the results using numerical computation. Then, we examine the impact of these non-idealities on the functionality and robustness of the probabilistic computing using Boolean logic implementation and image completion networks in the forward and backward modes of operation, respectively. For Boolean logic implementation, the weight matrix is found to be robust enough to allow p-bit network to retain its intended functionality despite non-idealities. Moreover, we show that there can be canceling effects of non-idealities, which can potentially be utilized in compensating reliability-induced degradation in a p-bit network. Additionally, using 1T-1MTJ-based p-bit implementation and SPICE simulations, we illustrate the applicability of the proposed model in analyzing and assessing the impact of non-idealities and process-induced variations on a p-bit network. We also demonstrate that statistical analysis techniques, such as Monte Carlo simulations, can help derive application-dependent constraints on the non-ideality of p-bits. These constraints will serve as critical design criteria for future p-bit implementations.

Reliable and fast channel estimation is crucial for next-generation wireless networks supporting a wide range of vehicular and low-latency services. Recently, deep learning (DL)-based channel estimation has been explored as an efficient alternative to conventional least-square (LS) and linear minimum mean square error (LMMSE) approaches. Most of these DL approaches have not been realized on system on chip (SoC), and preliminary study shows that their complexity exceeds the complexity of the entire physical layer (PHY). The high latency of DL is another concern. This article considers the design and implementation of deep neural network (DNN) augmented LS (LSDNN)-based channel estimation for preamble-based orthogonal frequency-division multiplexing (OFDM) PHY on SoC. We demonstrate the gain in performance compared with the conventional LS and LMMSE approaches. Via software–hardware codesign, word-length optimization, and reconfigurable architectures, we demonstrate the superiority of the LSDNN over LS and LMMSE for a wide range of signal-to-noise ratio (SNR), number of pilots, preamble types, and wireless channels. Furthermore, we evaluate the performance, power, and area (PPA) of the LS and LSDNN application-specific integrated circuit (ASIC) implementations in 45-nm technology. We demonstrate that word-length optimization can substantially improve PPA for the proposed architecture in ASIC implementations.

X-value combinational equivalence checking (XCEC) is a critical problem in verifying refinement-based logic optimizations and ensuring the correctness of low power design methodologies. The critical challenge in XCEC is to establish equivalence in a dramatically expanded search space. We can modify the traditional SAT-based Boolean combinational equivalence checking (CEC) methods to handle X-valued logic by adding an extra bit. However, the XCEC problem becomes more challenging when the two models are X-value equivalent because it involves considering the entire search space to prove the equivalence. Therefore, as an alternative, we propose to use SMT-based frameworks for XCEC by devising appropriate transformations. The proposed formulation allows the SMT solver to pre-process and simplify the encoded satisfiability problem internally. As a result, the SMT-based framework for XCEC is more efficient than a pure SAT-based XCEC, especially for cases in which the revised model is a valid refinement of the given golden model. We have used Cryptominisat5 to implement SAT-based XCEC and STP (with Cryptominisat5 as an internal SAT solver) to implement SMT-based XCEC. Using ICCAD 2020 benchmark suite, we demonstrate that, on an average SMT-based approach is 2.5× faster than the SAT-based approach for X-value equivalent cases.

Bipolar Impact Ionization MOSFETs (BI-MOS) are promising devices because of abrupt OFF-ON transition and lower breakdown voltage compared to a conventional I-MOS. Nevertheless, the breakdown voltage of a BI-MOS is $\sim 2.8 V$ and needs to be further reduced. In this paper, using a calibrated simulation model, we demonstrate that by employing an optimum gate–source underlap, 25% reduction in the breakdown voltage can be obtained. The gate–source underlap creates a spike in the electric field in regions where impact ionization is initiated. Thus, it aids the breakdown phenomenon and reduces the breakdown voltage. Furthermore, we employ the proposed technique on a double gate bipolar junctionless impact ionization MOSFET (DG BJI-MOS). We demonstrate that a 17% reduction in the breakdown voltage can be obtained by gate–source underlap and the breakdown voltage in the proposed device reduces to $\sim 1.5 V$.

Traditional timing analysis employs a delay model that assumes only a single input switches for a gate during a transition, while all side inputs are held constant to noncontrolling values. However, ignoring the impact of multiple-input switching (MIS) can lead to either an overestimation or an underestimation of a gate delay. In this article, we examine the impact of MIS in the delay of different types of gates under varying conditions of load, slew, and temporal distance of signals at the inputs. We model the impact of MIS by deriving a corrective measure that should be applied to the conventional single-input switching (SIS) delay under different conditions. We call this corrective measure as MIS-SIS difference (MSD). In this work, we have evaluated polynomial regressions, support vector regression, and artificial neural networks (ANNs) to model MSD. Additionally, we integrate the ANN-based MSD model into existing timing libraries and employ them in carrying out MIS-aware timing analysis. We test the proposed methodology on some benchmark circuits and demonstrate that the proposed technique can improve the accuracy of timing analysis effectively. For example, for ISCAS'85 C17 circuit having short paths, under the MIS scenario, traditional SIS-based delay differs from the corresponding SPICE-computed delay by as large as 120%. However, the delay computed using the proposed methodology under the MIS scenario for the same circuit differs from the SPICE-computed delay by less than 3%. Additionally, the runtime overhead of the proposed methodology during timing analysis is negligible.

In this paper, we develop an analytical model based on Enz Krummenacher Vittoz (EKV) current equations to assess the impact of temperature and supply voltage (VDD) variations in circuits operating in near-threshold voltage (NTV) regime. Using the proposed model, we derive parameters that can be optimized to reduce the impact of these variations on devices operating in the NTV regime and highlight the dominant role of the inversion coefficient of the EKV equations. Further, we show that, instead of operating circuits such as a CMOS inverter very close to the threshold voltage (VTH.), it is beneficial to operate these circuits 3 - 4kT/q above the VTH. At these voltages, the impact of the temperature variations on the delay is minimized and the impact of VDD variations on delay is 0.7x lower than when operated at VDD =VTH. Additionally, compared to the super-threshold operation, the power consumption reduces by 5x and the delay increases by 5x. The results presented in this paper can be employed in estimating the increase in the time margins required when a circuit is migrated from the super-threshold operation to the near-threshold operation.