Convolutional Neural Networks (CNNs) are employed in a broad range of classification tasks. Despite CNNs have reached high accuracy, they have high computational complexity, so employing this method in many applications such as internet of things (IoT) is challenging. To overcome this challenge, CNN hardware accelerators are proposed. As the main activation function employed in the CNNs is ReLU, a large portion of the output becomes zero. Therefore, sparse CNN accelerators are proposed to reduce the computational complexity. Recent studies show that, rather than employing sparse CNN accelerators, it would be ideal to predict the zero outputs and remove the corresponding computations. In this paper, we propose the iMAC accelerator to bypass ineffectual computations (a computation leads to zero). For this purpose, we propose a prediction unit that determines ineffectual computations without accuracy loss. Then we propose a dataflow to bypass ineffectual computations. The results show that by increasing 12% of area and 18% power overhead, iMAC achieves 2.31× speedup and 1.95× energy efficiency without any accuracy loss. With 3% accuracy loss, it further improves the speed and the energy by 2.94× and 2.49×, respectively. Moreover, compared to the previous prediction method, our method achieves higher speedup and improvement.

Hyperdimensional (HD) computing is a brain-inspired learning method that is widely employed in resource-constrained applications, such as the Internet of Things (IoT) regarding its lightweight computation. Although HD computing has high efficiency in the IoT applications, it suffers from high computation due to the large vector size. Thus, several studies are proposed to speedup and increase the efficiency of HD computing. In this work, we propose a method to process HD computing called PartialHD. Our method divides a long hypervector into multiple partial vectors and processes each vector separately. In the retraining phase, this method improves accuracy up to 1.93%. Moreover, by employing our proposed method in the retraining and inference, only a few partial vectors participate and this causes the computational overhead reduces in these phases. The evaluation shows that our method processes on average 22.2% and 36.23% of the entire hypervectors with negligible accuracy loss in inference and retraining, respectively. Furthermore, we propose two general architectures (lightweight and high-speed), which accelerate partial vector computations on different FPGA platforms. The result shows that the lightweight architecture can accelerate HD computing on resource-constrained FPGAs such as Artix while the high-speed architecture has$4.72\times $higher throughput than the lightweight architecture.

Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an open-source instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to reduce the computational overhead at the HD inference phase, we introduce a pruning method to remove the ineffectual dimensions. The proposed pruning method can reduce the dimension from 10k to 1k with negligible accuracy loss. Second, an ISA extension for RI5CY is proposed to compute the HD inference efficiently. Experimental results indicate that RISC-HD adds$1.42\times $area overhead to the RI5CY core; however, it consumes only 2932 slices on the Artix-7 FPGA, which is suitable for resource-constrained devices. Additionally, RISC-HD improves the total clock cycle by$7.48\times $compared to the RI5CY core and$6.17\times $compared to ARM Cortex-M4 in the ISOLET data set. Moreover, RISC-HD achieves$7.22\times $energy efficiency compared to the RI5CY core.

Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture outperforms state-of-the-art software implementations, which run on Intel’s Core-i5. Our evaluation results on FPGA show that this architecture reduces the Legendre calculation time by$2.56\times $compared to software implementations on Core-i5. On the other hand, the low-area architecture consumes only 5489 slices on the Artix-7 FPGA and is suitable for resource-constrained devices. Moreover, our ASIC implementation results indicate that the low-area architecture consumes 97.56K gates to implement and requires$4.01~mW$to operate on 50 MHz. The high-frequency architecture increases the frequency by$1.72\times $over the high-speed architecture and achieves 200 MHz frequency on FPGA.

Solid-State Drives (SSDs) are recently employed in enterprise servers and high-end storage systems in order to enhance performance of storage subsystem. Although employing high speed SSDs in the storage subsystems can significantly improve system performance, it comes with significant reliability threat for write operations upon power failures. In this paper, we present a comprehensive analysis investigating the impact of workload dependent parameters on the reliability of SSDs under power failure for variety of SSDs (from top manufacturers). To this end, we first develop a platform to perform two important features required for study: a) a realistic fault injection into the SSD in the computing systems and b) data loss detection mechanism on the SSD upon power failure. In the proposed physical fault injection platform, SSDs experience a real discharge phase of Power Supply Unit (PSU) that occurs during power failure in data centers which was neglected in previous studies. The impact of workload dependent parameters such as workload Working Set Size (WSS), request size, request type, access pattern, and sequence of accesses on the failure of SSDs is carefully studied in the presence of realistic power failures. Experimental results over thousands number of fault injections show that data loss occurs even after completion of the request (up to 700ms) where the failure rate is influenced by the type, size, access pattern, and sequence of IO accesses while other parameters such as workload WSS has no impact on the failure of SSDs.