Bo-Ren Chen

dblp:218/3268 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2022
0000-0002-7596-9145ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.412019
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Electronic design automation
hardware verification and test
0.412019
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Electronic design automation › hardware verification and test › design for testability
scan chain design
0.412019
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Electronic design automation › hardware verification and test
test data compression
0.412019
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019

Methods — techniques the papers use, named apart from their topics

single-input compression · 0.4scan chain partitioning · 0.4clock gating · 0.4broadcast scan · 0.4
YearPublicationVenuePosition
2022 Additive Manufacturing for Tissue Engineering Applications in a Temperature-Controlled Environment
abstract
In recent years, with the combination of tissue engineering and additive manufacturing technologies, the possibility of fabricating scaffolds with porosity and complex structure has been improved. Since the properties of most biomaterial inks are influenced by temperature and thereby affect the quality of the scaffolds, a controlled printing environment is very important. This study focuses on temperature monitoring from the nozzle to the working platform. A compact heating jacket is developed to heat the needle and sense its temperature inside the nozzle. It makes it very different from common cartridge heating mechanisms. Moreover, a semi-closed printing environment composed of an air curtain and temperature circulation device is developed to create a stable cooling environment. It improves the uniformity of the work platform and increases by 50% the cooling time efficiency. To demonstrate the robustness for a wide range of temperatures, this study presents two experiments of printing two biomaterial inks at body and low temperatures, respectively.
Wei-Chih Tseng, Chao-Yaug Liao, Bo-Ren Chen, Luc Chassagne, Barthelemy Cagneau
IROS3
2019 On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains
abstract
This paper presents a novel test architecture that combines the advantages of high-quality deterministic scan-based test and low-cost built-in self-test. The main idea is to record (store) all required compressed test data in a novel scan chain structure, and extract and decompress them during testing. This requires a very high compression ratio to obtain a low test data volume, that is, smaller than the number of scan cells in the circuit under test. To achieve such a high compression ratio, we propose a novel compression method that combines broadcast scan as well as a tailored single-input compression architecture. We also utilize the concept of scan chain partitioning and clock gating to reduce the test time and test power. An on-chip test controller is employed to automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external automatic test equipment. Experimental results show that our method is well suitable for multicore designs. For example, experiments on the 8-core open-source OpenSPARC T2 processor with 5.7M gates show that all required test data for 100% testable stuck-at fault coverage can be stored in just 59.4% of the scan cells of the processor. Experimental results for transition faults are also presented, which show that more identical cores are needed in order to store all test data for transition faults. We also discuss how to extend this paper to address fault diagnosis and engineering change order problems.
Kuen-Jong Lee, Bo-Ren Chen, Michael A. Kochte
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2