The security of the FPGA cloud has become a major concern for both industry and academia due to its widespread use in many vital domains. In this article, we expose a hardware vulnerability in the FPGA cloud and demonstrate a covert and efficient denial-of-service (DoS) attack method that severely threatens the security of the FPGA cloud. First, we adopt a flip-flop-based ring oscillator (RO) to construct an adaptive ring oscillator network (RON). Second, we devise a power and temperature-based resource adjustment algorithm to decide the maximum number of ROs in the adaptive RON. By constraining the size of the adaptive RON, the power and the thermal footprint of the attack process can be reduced. Finally, we design an adaptive frequency sweeping algorithm to automatically search for an effective frequency and perform a successful attack on the FPGA. To validate our method, we conduct exemplary attacks on FPGAs. The results reveal that our method can successfully bypass the design rule checking (DRC) and security measures of the FPGA cloud to crash the FPGA. Besides high-end FPGAs, we demonstrate our method is suitable for some FPGAs with moderate performance. Furthermore, we discuss the impact of the number of ROs and the duty cycle on the proposed method.

With the widespread use of FPGA clouds in high-end fields such as artificial intelligence, its security issues have become a major focus for both academia and industry. In this paper, we propose a covert Denial-of-Service (DoS) attack method that specifically targets commercial FPGA clouds, posing a serious threat to the availability of FPGA clouds. Firstly, we design a malicious ring oscillator network (RON) that can evade the design rule checking of FPGA clouds. Then, we propose a resource adjustment algorithm to determine the maximum number of ring oscillators (ROs) in the RON while satisfying the FPGA's power and on-chip temperature constraints to guarantee the covertness of the attack process. Finally, we manually search for the efficient attack frequency for the RON to attack FPGAs. To validate our method, we perform DoS attacks on XVU9P and 10AX115 FPGAs. The results demonstrate that our method can evade the security measures of FPGA clouds and successfully crash FPGAs.

We consider a holistic approach for dual‐access cognitive small cell (DACS) networks, which uses the LTE air interface in both licensed and unlicensed bands. In the licensed band, we consider a sensing‐based power allocation scheme to maximize the sum data rate of DACSs by jointly optimizing the cell selection, the sensing operation, and the power allocation under the interference constraint to macrocell users. Due to intercell interference and the integer nature of the cell selection, the resulting optimization problems lead to a nonconvex integer programming. We reformulate the problem to a nonconvex power allocation game and find the relaxed equilibria, quasi‐Nash equilibrium. Furthermore, in order to guarantee the fairness of the whole system, we propose a dynamic satisfaction‐based dual‐band traffic balancing (SDTB) algorithm over licensed and unlicensed bands for DACSs which aims at maximizing the overall satisfaction of the system. We obtain the optimal transmission time in the unlicensed band to ensure the proportional fair coexistence with WiFi while guaranteeing the traffic balancing of DACSs. Simulation results demonstrate that the SDTB algorithm could achieve a considerable performance improvement relative to the schemes in literature, while providing a tradeoff between maximizing the total data rate and achieving better fairness among networks.