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Yizhang Wu

dblp:219/0384 · DBLP profile ↗
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3ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Security and privacy · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 60% Authentication and access control · 40%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 67% Electronic design automation · 33%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computational science and engineering · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › hardware reverse engineering
integrated circuit reverse engineering
0.412020
Reverse Engineering for 2.5-D Split Manufactured ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Authentication and access control › user authentication
lightweight authentication
0.412020
SLATE: A Secure Lightweight Entity Authentication Hardware Primitive · IEEE Trans. Inf. Forensics Secur. 2020
Hardware security and side channels › hardware security primitives
physical unclonable function
0.412020
SLATE: A Secure Lightweight Entity Authentication Hardware Primitive · IEEE Trans. Inf. Forensics Secur. 2020
Hardware security and side channels › hardware security primitives › physical unclonable function
strong PUF
0.412020
SLATE: A Secure Lightweight Entity Authentication Hardware Primitive · IEEE Trans. Inf. Forensics Secur. 2020
Authentication and access control
user authentication
0.412020
SLATE: A Secure Lightweight Entity Authentication Hardware Primitive · IEEE Trans. Inf. Forensics Secur. 2020
Electronic design automation
hardware verification and test
0.412020
Reverse Engineering for 2.5-D Split Manufactured ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Computational science and engineering
materials science
0.312025
Wafer-scale fabrication of monolayer MoS2 films for two-dimensional electronic devices via multitube atmospheric-pressure chemical vapor deposition · Sci. China Inf. Sci. 2025

Methods — techniques the papers use, named apart from their topics

chemical vapor deposition · 1.7satisfiability modulo theories · 0.9grouping algorithm · 0.9boolean satisfiability · 0.9challenge-response pair verification · 0.4
YearPublicationVenuePosition
2025 Wafer-scale fabrication of monolayer MoS2 films for two-dimensional electronic devices via multitube atmospheric-pressure chemical vapor deposition
Zixuan Cheng, Dingyi Yang, Yizhang Wu, Jiateng Zhang, Mingwen Zhang, Xuetao Gan, Genquan Han
Sci. China Inf. Sci.4
2020 Reverse Engineering for 2.5-D Split Manufactured ICs
abstract
Integrated circuit (IC) split manufacturing has been shown to be one of the most effective protection schemes to prevent reverse engineering from malicious foundries. Among the existing split manufacturing approaches, the 2.5-D split manufacturing using silicon interposer has much less fabrication and testing costs compared to layer splitting approaches. In this article, we propose a Boolean satisfiability (SAT)-based attack to reconstruct the wire connections of the 2.5-D split manufacturing netlists. Our SAT-based attack can fully reconstruct the missing wires between modules with 100% correctness and therefore the functionality of the chip can be completely reverse engineered. In addition, we show that the runtime of attack is significantly reduced compared to existing 2.5-D split manufacturing SAT attacks by applying grouping hints obtained from a satisfiability modulo theories (SMTs)-based grouping algorithm, which is purely depending on the circuit functionality, so no physical defensive mechanisms can prevent such attack. In our experiments, we show that our grouping algorithm can speed up the existing SAT attack runtime by more than 1000× and can successfully reverse engineer reasonable size benchmarks even when the split nets contains more than one fanouts and the total cut size is close to 1000.
Wei-Che Wang, Yizhang Wu, Puneet Gupta 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2020 SLATE: A Secure Lightweight Entity Authentication Hardware Primitive
abstract
Lightweight cryptography has become more and more important in recent years because of the rise of the Internet of Things (IoT) and usage of smart mobile devices. In this paper, we propose a novel secure lightweight entity authentication hardware primitive called SLATE, where its area is about 50% to more than 3X smaller than existing lightweight ciphers and strong physical unclonable functions (PUFs), respectively. Even though the authentication of SLATE is done through challenge response pair (CRP) verification similar to strong PUFs, the source of the key for SLATE must be coming from any existing secret key storage used for any ciphers. A main advantage of SLATE over most existing strong PUFs being an entity authentication primitive is that SLATE is resistant to known attacks to strong PUFs or logic obfuscations, such as model building attacks and Boolean satisfiability (SAT) attacks. Furthermore, we show that the implementation cost of SLATE with a 176-bit key and 244 CRPs is only 663 gate equivalents (GEs). Compared with lightweight ciphers and existing secure strong PUFs, we show that SLATE is a practical security primitive for resource constrained systems for its extremely small footprint and security. Finally, we show that SLATE is information theoretically secure when valid CRPs are communicated through insecure channels.
Wei-Che Wang, Yair Yona, Yizhang Wu, Suhas N. Diggavi, Puneet Gupta 0001
IEEE Trans. Inf. Forensics Secur.3