This paper presents a compact configuration of memtranstor (MT), a new memory element having direct relation between magnetic flux (φ) and charge (q). The proposed configuration offers a simple architecture as it is designed without the need of any multiplier or any other complex component. This emulator has been realized by employing one operational transconductance amplifier (OTA), one current differencing transconductance amplifier (CDTA), and one voltage differencing current conveyor (VDCC) along with a few passive components. The emulator captures the fundamental relationship between φ and q, enabling the realization of distinctive pinched hysteresis loops under sinusoidal excitation, a hallmark of memtranstive behavior. It is designed to operate at a supply voltage of ±1.25 V. The circuit offers tunability through the variation in biasing voltages ensuring flexibility for a wide range of applications. The accuracy and dynamic characteristics of the proposed architecture are verified through mathematical analysis and LTSpice simulations with a 180 nm CMOS model. To assess the behavior of the proposed emulator in real environment, process-voltage-temperature analysis has been carried out followed by the designing of full custom layout in an area of 4464.88 μm 2 . Furthermore, non-ideal analysis has been carried out considering the parasitic elements at various terminals of the blocks employed in the circuit design. Additionally, to prove the practical feasibility of the proposed circuit, its operation has been confirmed by macro-models of the designated ICs followed by the bread-board implementation using commercial ICs under ±12 V supply voltage. To demonstrate practical utility, the emulator is employed in two key applications: an artificial synapse for neuromorphic systems and a nonlinear chaotic oscillator, both showcasing its relevance for next-generation memory-driven analog computing. The proposed design stands out due to its low component count, compact design, and ease of integration, making it a promising candidate for emerging fields like neuromorphic engineering and chaos-based systems. Furthermore, it provides valuable insights for future research in MT-based nonlinear dynamics and holds significant potential for advancing MT driven applications in neuromorphic computing and beyond.

In the current scenario, the utilization, and advancement of security algorithms in communication models have been increased. The use of chaotic circuit-based secure algorithms can give a new direction to develop a highly secure communication model. Security in any communication model can be provided by various available methods. The main feature of any security method is to introduce randomness at every step of the algorithm. Generally, the security algorithms deal with random numbers that are generated using a random number generator with predefined logic in the conventional secure communication model. In this article, the chaotic behavioral circuit is used to handle the randomness. The three main classifications of security control are management security, operational security, and physical security controls. The chaotic behavior of high-dimensional Chua’s circuit has been used to implement these three security controls. The challenging task is to design and deploy$(n,k$) secret sharing scheme using Chua’s oscillator. The novel authenticator code function based on Chua’s oscillator is proposed in this paper. This authenticator code function is having almost the same characteristics as of hash code, but with a higher degree of security.