Geoffrey Bruce Jackson

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3ranked-venue papers

2as first author

0since 2021 · last 1995

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence 1 paper		Robot navigation and mapping · 100%
Computer architecture, parallel and distributed computing, and storage systems 1 paper		Hardware accelerators and domain-specific architectures · 100%

Topics — the 1 heaviest of 2, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Hardware accelerators and domain-specific architectures neural network hardware	0.0	1	1995	Competence Acquisition in an Autonomous Mobile Robot using Hardware Neural Techniques · NIPS 1995

Methods — techniques the papers use, named apart from their topics

hardware neural network · 0.0

Year	Publication	Venue	Position
1995	Competence Acquisition in an Autonomous Mobile Robot using Hardware Neural Techniques Geoffrey Bruce Jackson, Alan F. Murray	NIPS	1
1994	Pulse Stream VLSI Neural Systems: Into Robotics abstract This paper presents for the first time a new chip, EPSILON II, which improves the electrical characteristics, interface flexibility and general architecture of the original EPSILON device. A system level framework is presented, built around the EPSILON II device, which allows the development of pulse stream neural systems for real-world applications. As a "first instance" example to demonstrate this an autonomous "instinct" driven robot is under construction.> Geoffrey Bruce Jackson, Alister Hamilton, Alan F. Murray	ISCAS	1
1993	Pulse Stream Vlsi Circuits And Systems: The Epsilon Neural Network Chipset abstract An analogue CMOS VLSI neural processing chip has been designed and fabricated. The device employs "pulse-stream" neural state signalling and is capable of computing some 360 million synaptic connections per second. In addition to basic characterisation results, the performance of the chip in solving "real-world" problems is also demonstrated. The experience gained from the development of this device has resulted in the design of a second "pulse-stream" chip with improved performance and features. It is anticipated that this second device will be integrated into a standard bus-based system and find early application in robotic control. Alister Hamilton, Stephen Churcher, Peter J. Edwards, Geoffrey Bruce Jackson, Alan F. Murray, H. Martin Reekie	Int. J. Neural Syst.	4