Carry tree sparseness is used in high-performance binary adders to achieve better energy-delay trade-off. To determine the energy optimal degree of sparseness, a detailed analysis is performed in this work. An analytical expression for the upper bound of sparseness is derived. The effect of increased sparseness on partial sum block and total energy is explored on 32-, 64-, 128-, and 256-bit adders. Higher degrees of sparseness in the carry generation block is achieved by employing parallel adders in the sum block instead of serial ripple carry adders. 64-bit adders with various sparseness degrees using leading addition algorithms are synthesized and optimized with a standard cell library in 45nm CMOS technology. Post layout simulations revealed that the optimal sparse carry tree adders provide up to 50% and 22% improvement in energy at same performance over full carry tree Kogge-Stone and Ladner-Fischer adder designs, respectively.

Energy-efficient serial and parallel multiplier structures are explored to see their suitability in the low and ultra low power design regimes. 16 × 16-bit serial and state-of-art parallel multipliers are compared in 45 nm CMOS. A multiplier structure is proposed by optimizing the architecture, gate sizes and the voltage supply. The proposed structure provides 15% more throughput as compared to two-cycle parallel multiplier with the same energy consumption for high speed applications. In the low speed design region, it provides 3.7X energy reduction compared to the serial multiplier.

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targets. In addition, novel 3:2 and 4:2 compressors are presented to save energy at the same target delay. The proposed compressors provide up to 20% energy reduction depending on the target delay at 65nm CMOS technology. Non-Booth multiplier implemented with the proposed compressors provides performance advantage as the voltage is scaled from its nominal value. Further, we examined all designs in 45nm, 32nm and 22nm CMOS technology nodes.

We present a systematic method for minimizing the energy of pipelined digital systems, through joint optimization of each pipeline stage and the system. A pipeline stage with a constant load can either be optimized for delay at a given input size, minimized for energy at a fixed delay, or have delay traded off for energy at a fixed input size. The results of these optimizations are combined to yield the design region for energy and delay. At the system level with a fixed throughput constraint, the sensitivities to input size and output load of all pipeline stages form the optimal energy criteria that provide a systematic method to minimize the total system energy. This method is applied to a media datapath, where we show up to 37% energy saving for a fixed performance. The minimal energy-delay curve of the system obtained through application of this method demonstrates similar characteristics as that of a single pipeline stage. With voltage scaling, the optimal solution displays a strong dependency between delay, energy, and supply voltage. The proper tradeoff between these entities makes a fundamental impact on efficient digital design.

Efficient adder design requires proper selection of a recurrence algorithm and its realization. Each of the algorithms: Weinberger's, Ling's and Doran's were analyzed for its flexibility in representation and suitability for realization in CMOS. We describe general techniques for developing efficient realizations based on CMOS technology constraints when using Ling's algorithm. From these techniques we propose two high-performance realizations that achieve 1 FO4 delay improvement at the same energy and 50% energy reduction at the same delay than existing Ling and Weinberger designs.

The formal analysis of parallelism and pipelining is performed on an 8-bit add-compare-select element of a Viterbi decoder. The results are quantified through a study of the delay and energy behaviors of gates and complex circuits due to supply scaling and circuit optimization on a modified test setup accounting for routing cost. The energy-throughput relationships of both pipelining and parallelism are characterized in connection to their corresponding depth and degree, showing clear advantages of pipelining over parallelism.

Design guidelines for low- and ultra low-power arithmetic units are presented. We analyze structures for addition in the energy-delay space to determine the most suitable for these regions of operations. This paper demonstrates that the use of more complex high-performance structures combined with scaling of the supply-voltage outperforms traditional low-power oriented designs in the low- and ultra low-power domain.

This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock frequency and impact of load imposed by the storage element to the clock distribution network. The presented analysis estimates the timing penalty and power savings of a system based on DETSE, and gives design guidelines for high-performance and low-power application. In addition, the paper presents a class of dual-edge triggered flip-flops with clock load, delay, and internal power consumption comparable to the fastest single-edge triggered storage elements (SETSE). Our simulated results show that by halving the clock frequency, dual-edge clocking strategy can save about 50% of the power consumed by the clock distribution network, and relax the design of clock distribution system, while paying virtually no penalty in throughput.

In this paper, we motivate the concept of comparing very large scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a need to make appropriate selection at the beginning of the design process. The estimation is quick, not requiring extensive simulation or use of computer-aided design tools, yet sufficiently accurate to provide guidance through various choices in the design process. We demonstrate the accuracy of the method by applying it to examples of high-performance 32- and 64-b adders in 100- and 130-nm CMOS technologies.

We talk about issues related to performance of arithmetic algorithms when implemented in silicon. Most of the algorithms in use today are based on old and antiquated methods of counting the number of logic gates in the critical path. This produces inaccurate and misleading results. In the course of VLSI processor design it is very important to choose the circuit topology that would yield desired performance for a given power budget. However, the performance and power of a chosen topology will be known only after the fact, i.e. after the design is finished. We motivate the concept of comparing VLSI structures based on their energy-delay trade-offs and we discuss techniques used for estimating the energy-delay space of various high-performance VLSI topologies.

We motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating the energy-delay space of various high-performance VLSI adder topologies. Further, we show that our estimates accurately represent tradeoffs in the energy-delay space for high-performance 32-bit and 64-bit processor adders in 0.13/spl mu/m and 0.10/spl mu/m CMOS technologies, with an accuracy of 8% in delay estimates and 20% in energy estimates, compared with simulated data.

A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower Energy-Delay Product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18um process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.

No abstract available.

A novel timing characterization for dual-edge triggered flip-flops is presented. This characterization takes into account the real overhead taken from the clock cycle by the flip-flops. Our study shows the correctness of these new metrics when compared against data-to-output delay. An example of the proposed delay characterization and comparison with conventional (data-to-output) metrics for dual-edge flip-flop design is given.

In power-constrained systems, the power efficiency of latches and flip-flops is pivotal. Characteristics of three selected latches and FFs were analyzed for their behavior under voltage scaling and different process corners in a 0.18um CMOS technology. The relative performance amongst the latches/FFs was consistent across the different supply voltages. At low-voltage power-delayproduct was degraded by about 25%. Energy-delay-product was approximately doubled at low-voltage – for all latches/FFs over all process corners. This result was smaller in comparison to the ideal voltage scaling characteristics mainly because the effects of velocity saturation were less severe at low voltage. All three designs suffered more due to process variation under low-voltage conditions. It was our interest to analyze the effect of large supply voltage variation as well as the typical process and environmental variation in bulk CMOS circuits. In assessing the quality of designs for the low power, both the designs and the evaluation methodology and criteria are equally important. We specifically focus on latches and flip-flops: an improved semi-dynamic flipflop (SDFF) [1], the sense-amplifier flip-flop (SAFF) [2] and the master-slave PowerPC latch [5]. Section 2 presents the effects of voltage scaling. Section 3 discusses modification to the test bench by Stojanovic and Oklobdzija [3]. Section 4 outlines the experiment. The choice of PMOS-to-NMOS ratio is presented in section 5. The simulated results are analyzed in section 6.

An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the tpLHand tpHLof the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.

The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 /spl mu/m CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary.

In this paper, design and VLSI implementation of an Early Branch Prediction (EBP) circuit, based on a variation of the Carry Look-ahead scheme is presented. The key features of this design are low area, high speed (2 [log n/2]+1), and high modularity. This design out performs all the EBP designs presented so far. For 64-bit word length the early branch prediction is obtained in 679 ps as simulated for 0.2 /spl mu/m technology under typical conditions. Simulation and layout results for 0.2 /spl mu/m CMOS technology show a 30% increase in speed with 25% decrease in area as compared, to recently published results.

In this paper we propose a set of rules for consistent estimation of the real performance and power features of the latch and flip-flop structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance applications.

In this paper we propose a set of rules for consistent estimation of the real performance and power features of the latch and flip-flop structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for low-power and high-performance applications.

We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. V.G. Oklobdzija et al. (1996) suggested a new approach, the Three-Dimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to produce a minimum delay PPRT using full adders. This is done by carefully modeling the relationship of the output delays to the input delays in an adder and, then, interconnecting the adders in a globally optimal way. Oklobdzija et al. suggested a good heuristic for finding the optimal PPRT, but no proofs about the performance of this heuristic were given. We provide a formal characterization of optimal PPRT circuits and prove a number of properties about them. For the problem of summing a set of input bits within the minimum delay, we present an algorithm that produces a minimum delay circuit in time linear in the size of the inputs. Our techniques allow us to prove tight lower bounds on multiplier circuit delays. These results are combined to create a program that finds optimal TDM multiplier designs. Using this program, we can show that, while the heuristic used by Oklobdzija et al. does not always find the optimal TDM circuit, it performs very well in terms of overall PPRT circuit delay. However, our search algorithms find better PPRT circuits for reducing the delay of the entire multiplier.

Multiply-accumulate is an important and expensive operation. It is frequently used in digital signal processing and video/graphics applications. As a result, any improvement in the delay for performing this operation could have a positive impact on clock speed, instruction time and processor performance. In this paper, we show how, by extending our view of a parallel multiplier, we can apply recent innovations in parallel multiplier design to multiply-accumulators. This application results in multiply-accumulators that are as fast as multipliers of the same size (these multipliers have been shown to result in provably optimal delays faster than current designs). This allows a single (optimal multiply-accumulate) circuit to be used for both operations without delay penalty. As a result, multiply-accumulate can be efficiently and effectively implemented as an instruction in RISC CPUs. Additionally, the circuit design reduces the number of devices needed over current fast multiplier designs, so that real estate and power savings also result.

In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings in the adiabatic mode versus the non-adiabatic mode at clock frequencies up to about 40 MHz.

This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1 /spl mu/ CMOS ASIC technology.

We present new design and analysis techniques for the synthesis of fast parallel multiplier circuits. V.G. Oklobdzija, D. Villeger, and S.S. Lui (1995) suggested a new approach, the three dimensional method (TDM), for partial product reduction tree (PPRT) design that produces multipliers which outperform the current best designs. The goal of TDM is to produce a minimum delay PPRT using full adders. This is done by carefully modelling the relationship of the output delays to the input delays an an adder, and then interconnecting the adders in a globally optimal way. Oklobdzija, et. al. suggested a good heuristic for finding the optimal PPRT, but no proofs about the performance of this heuristic were given. We provide a formal characterization of optimal PPRT circuits and prove a number of properties about them. For the problem of summing a set of input bits within the minimum delay, we present an algorithm that produces a minimum delay circuit in time linear in the size of the inputs. Our techniques allow us to prove tight lower bounds on multiplier circuit delays. These results are combined to create a program which finds optimal TDM multiplier designs.>

In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier.>

In this paper, an SRAM-DRAM combination memory is used as an on-chip cache memory. The SRAM portion is considered to be the first level cache and the DRAM portion is considered to be the second level cache. Curves are derived for the optimal SRAM and DRAM sizes with memory access time optimized. These curves do vary with the amount of fixed on-chip area available, with different cell size ratios of DRAM to SRAM and with varying DRAM access times. The optimal amount of SRAM, or first level cache, is consistently seen to be much smaller then the general trend toward a large first level cache. For instance, if the on-chip area available for cache could contain 256 K of SRAM then only about 16 K of SRAM should exist along with 2.5 M of DRAM as second level cache for optimal usage of that area.>

A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both: logic synthesis and an algorithmic approach. The algorithmic implementation is compared with the results obtained using modern logic synthesis tools in the same 0.6 /spl mu/m CMOS technology. The implementation based on an algorithmic approach showed an advantage compared to the results produced by the logic synthesis. ECL implementation of the 64 bit LZD circuit was simulated to perform in under 200 ps for nominal speed.>

The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions.>

The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the proposed delay model, critical path delay is calculated taking into account not only the intrinsic gate delays but also the fanin and fanout contributions.>

An architecture for a single-chip VLSI implementation of a Wigner distribution signal processor is presented. ASIC implementation in CMOS technology is considered with complexity of 65000 gates, achieving a maximum throughput of 12 K 16-bit samples per second. The architecture takes advantage of the high level of integration and low power consumption achievable with CMOS technology thus eliminating clock skew and off-chip delays associated with chip-crossing penalties. By integrating the Wigner processor on the single chip, the implementation is made practical and attractive for processing acoustic signals.>

An efficient scheme for carry propagation in an ALU implemented in n-MOS technology is presented. An algorithm that determines the optimum division of the carry chain of a parallel adder for various data path sizes is developed. This yields an implementation of a fast ALU which due to its regular structure occupies a modest amount of silicon. The speed of the implementation described is comparable to the carry look-ahead scheme. Our method is based on the optimization of the carry path implemented in n-MOS technology but the results can be applied to other technologies.

In this correspondence a systematic derivation of an on-line square root algorithm is presented. The algorithm operates on variables represented in the normalized radix r floating-point system in a digit-by-digit fashion with an on-line delay of 1. The approach used in deriving the square root algorithm is described in detail. The basic characteristics of hardware-level implementation are also discussed.