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Tong Chen 0010

dblp:22/1512-10 · DBLP profile ↗
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5ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization › compiler optimization
speculative optimization
0.012004
A compiler framework for speculative optimizations · ACM Trans. Archit. Code Optim. 2004
Compilers and program optimization › intermediate representation
static single assignment form
0.012004
A compiler framework for speculative optimizations · ACM Trans. Archit. Code Optim. 2004
Processor architecture and microarchitecture › instruction set architecture
EPIC architecture
0.012004
A compiler framework for speculative optimizations · ACM Trans. Archit. Code Optim. 2004
Processor architecture and microarchitecture
speculative execution
0.012003
A compiler framework for speculative analysis and optimizations · PLDI 2003

Methods — techniques the papers use, named apart from their topics

strength reduction · 0.1register promotion · 0.1partial redundancy elimination · 0.1alias profiling · 0.1compiler framework · 0.1
YearPublicationVenuePosition
2004 Data Dependence Profiling for Speculative Optimizations
Tong Chen 0010, Xiaoru Dai, Wei-Chung Hsu, Pen-Chung Yew
CC1
2004 A compiler framework for speculative optimizations
abstract
Speculative execution, such as control speculation or data speculation, is an effective way to improve program performance. Using edge/path profile information or simple heuristic rules, existing compiler frameworks can adequately incorporate and exploit control speculation. However, very little has been done so far to allow existing compiler frameworks to incorporate and exploit data speculation effectively in various program transformations beyond instruction scheduling. This paper proposes a speculative static single assignment form to incorporate information from alias profiling and/or heuristic rules for data speculation, thus allowing existing frameworks to be extended to support both control and data speculation. Such a general framework is very useful for EPIC architectures that provide run-time checking (such as advanced load address table ) on data speculation to guarantee the correctness of program execution. We use SSAPRE as one example to illustrate how to incorporate data speculation in partial redundancy elimination, register promotion, and strength reduction. Our extended framework allows both control and data speculations to be performed on top of SSAPRE and, thus, enables more aggressive speculative optimizations. The proposed framework has been implemented on Intel's Open Research Compiler. We present experimental data on some SPEC2000 benchmark programs to demonstrate the usefulness of this framework.
Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan
ACM Trans. Archit. Code Optim.2
2003 Speculative Register Promotion Using Advanced Load Address Table (ALAT)
abstract
The pervasive use of pointers with complicated patterns in C programs often constrains compiler alias analysis to yield conservative register allocation and promotion. Speculative register promotion with hardware support has the potential to more aggressively promote memory references into registers in the presence of aliases. This paper studies the use of the advanced load address table (ALAT), a data speculation feature defined in the IA-64 architecture, for speculative register promotion. An algorithm for speculative register promotion based on partial redundancy elimination is presented. The algorithm is implemented in Intel's open research compiler (ORC). Experiments on SPEC CPU2000 benchmark programs are conducted to show that speculative register promotion can improve performance of some benchmarks by 1% to 7%.
Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew
CGO2
2003 A compiler framework for speculative analysis and optimizations
Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan
PLDI2
1991 A New Synchronization Mechanism
Tong Chen 0010, Chuanqi Zhu
ICPP (1)1