The increasing deployment of artificial intelligence (AI) at the edge, particularly convolutional neural networks (CNNs) in resource-constrained devices, has created new challenges for ensuring system reliability and safety. Market analysts project a 21% annual growth rate in the edge AI market size over the next five years. These devices are being used in safety-critical applications such as autonomous vehicles, industrial control systems, and medical devices, where malfunctions due to radiationinduced soft errors can have severe consequences, ranging from degraded performance to life-threatening situations. Soft errors, caused by energetic particles, can corrupt data and instructions, resulting in unpredictable system behaviour. To meet safety standards in these domains, reliability engineers must proactively explore and implement efficient mitigation solutions during the initial design cycle.

Machine learning (ML) algorithms offer solutions across diverse domains, including resource-constrained devices. Despite advances in performance optimization and reduced-precision implementations, ML susceptibility to soft errors from radiation remains unclear. This work uses virtual platforms (VPs) to conduct a comprehensive soft error reliability assessment, at early design phases, of ML algorithms for Arm processors. The test strategy integrates confidence metrics, extensive fault injection (FI) campaigns, application profiling, and fault classifications. The main goals comprise (i) analyzing the consistency of SOFIA, a JIT-based framework, against event-driven simulators (mean mismatch ±4%, worst-case ±8%) and (ii) investigating correlations between FI results, NN-optimized kernels, and reduced-precision CNNs for IoT devices (up to 60% critical faults), aiming to promote software-based mitigation techniques (up to 98% critical faults mitigated). Results covering over 14.8 million FIs highlight SOFIA’s consistency, offering insights into balancing performance and reliability in multithreaded IoT edge platforms.

Automotive networks are crucial for ensuring safety as the number of Electronic Control Units (ECUs) grows to support vehicle intelligence. The Controller Area Network (CAN) is commonly used for efficient in-vehicle communication among ECUs. However, its broadcast nature and lack of a dedicated security layer make it vulnerable to attacks. This paper proposes a novel CAN bus Intrusion Detection System (IDS), named BNN-based IDS (BIDS), which efficiently provides both unknown attack detection and known attack classification using a hierarchical two-stage Binarised Neural Network (BNN) and Generative Adversarial Network (GAN). BIDS was validated on three datasets, and its implementation achieves an average inference time of less than 0.170 ms with minimal resource utilisation on a low-cost Field Programmable Gate Array (FPGA). This rapid inference speed enables real-time inference on individual CAN messages using a sliding window technique, eliminating the need to wait for multiple accumulated CAN messages required for data preprocessing. Evaluation metrics demonstrate that our IDS achieves high accuracy in both identifying unseen attacks and categorising known attacks. Furthermore, our FPGA implementation consumes merely 2.09 W, which is a 57% reduction compared to a cutting-edge FPGA-based IDS that is capable of detecting unknown attacks using the same dataset.

Security and reliability problems in edge devices can become the Achilles’ heel for their massive use in Internet of Things (IoT) systems. While most works address security by implementing lightweight cryptographic algorithms, this paper is the first to assess the soft error reliability of lightweight cryptographic algorithms targeting IoT edge devices. This paper performs soft error analysis for ten lightweight cryptographic algorithms considering two compilers and running on top of an IoT-ready commercial processor model (i.e. Arm Cortex-M7). From the ten lightweight cryptographic algorithms, IDEA shows the best trade-off between reliability and number of instructions. Index Terms-Lightweight Cryptographic (LWC) Algorithms, Soft Error, Reliability, Internet of Things (IoT), Edge Devices.

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety-critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors during the initial design cycle.

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety–critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors at the initial design cycle. This paper presents SOFIA, a framework that integrates: (i) a set of fault injection techniques that enable bespoke inspections, (ii) machine learning methods to correlate soft error results and system architecture parameters, and (iii) mitigation techniques, including: full and partial triple modular redundancy (TMR) as well as a register allocation technique (RAT), which allocates the critical code (e.g., application’s function, machine learning layer) to a pool of specific processor registers. The proposed framework and novel variations of the RAT are validated through more than 1739k fault injections considering a real Linux kernel, benchmarks from different domains and a multi-core Arm processor.

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

To achieve a substantial reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper proposes a low-cost system-level soft error mitigation technique, which allocates the critical application function to a pool of specific general-purpose processor registers. Both the critical function and the register pool are automatically selected by a developed profiling tool. The proposed technique was validated through more than 320K fault injections considering a Linux kernel, different benchmarks and two multicore ARM processors. Results show that our technique significantly reduces the code size and performance overheads while providing reliability improvement, w.r.t. the Triple Modular Redundancy (TMR) technique.

Automotive systems are integrating artificial intelligence and complex software stacks aiming to investigate the real world, make decisions and perform actions without human input. The occurrence of soft errors in such systems can lead to wrong decisions, which might ultimately incur in life losses. This paper focuses on the assessment of the soft error susceptibility of a real automotive application (with up to 180 billion instructions) considering Linux kernel, multicore processor, and different cross-compilers. Results collected from extensive simulations show that the compiler can influence the reliability of the system.

Electronic computing systems are integrating modern multicore processors and GPUs aiming to perform complex software stacks in different life-critical systems, including health devices and emerging self-driving cars. Such systems are expected to experience at least one soft error per day in the near future [1], which may lead to life-threatening failures. This paper presents four novel non-intrusive fault injection techniques that enable full fault injection control and inspection of multicore systems behavior in the presence of faults. Proposed techniques were integrated into a fault injection framework and verified through a real automotive case study with up to 43 billions instructions. Results show that isolating critical application functions can lead to a more efficient soft error analysis with a reduction of masked faults in up to 28%.

Emerging electronic computing systems are becoming more vulnerable to the occurrence of soft errors in different system components (e.g., processors, memory, GPUs). To assess more useful information of the soft error reliability of multicore systems, this work proposes the extension of a fault injection framework, by including tools to trace and profile applications behavior under the presence of faults. Our approach is up to 10 times faster than simply parsing the application's disassembly, and it can show that, when affected by a fault, memory instructions are one of the safest in terms of crashing.

To take advantage of the performance enhancements provided by multicore processors, new instruction set architectures (ISAs) and parallel programming libraries have been investigated across multiple industrial segments. This paper investigates the impact of parallelization libraries and distinct ISAs on the soft error reliability of two multicore ARM processor models (i.e., Cortex-A9 and Cortex-A72), running Linux Kernel and benchmarks with up to 87 billion instructions. An extensive soft error evaluation with more than 1.2 million simulation hours, considering ARMv7 and ARMv8 ISAs and the NAS Parallel Benchmark (NPB) suite is presented.

Software reliability is an essential design metric in emerging large-scale multiprocessor embedded systems. Designers should identify soft error susceptibility of multiple applications executing in parallel early in the design time to ensure reliable system operation. This work proposes a non-intrusive fault injection engine that enables to conduct bespoke soft error analysis, allowing to identify and understand the soft error propagation through the processing elements (PEs). The proposed fault injection campaign evaluates the impact of soft errors considering real benchmarks in an RTL model of a distributed-memory NoC-based multiprocessor. Experiments demonstrate that 19% of soft errors are propagated to other PEs, where 31.6% of them led to erroneous computation and 58.4% to a system crash. Thus, the fault analysis must consider not only its local effect on the processor and memory but also how the fault propagates to other system components.

Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. Underlying models are traditionally meant for static scenarios where all communicating entities and their intercommunication patterns are known a priori by the software engineer. The systems design following such programming models became complex due to dynamic behavior of applications at runtime. The goal of this work is to incorporate a publish-subscribe programming model to an MPSoC framework to decouple, in the time and space, the application development. The modified MPSoC framework is composed of a FreeRTOS kernel running on homogeneous processing elements distributed into a network-on-chip. The results present reduction around of 2% to 30% in DTW application execution time, and low overhead in memory footprint when comparing the original MPI primitives with the publish-subscribe programming model.

A large portion of existing multithreaded embedded software has been programmed according to symmetric shared memory platforms where a monolithic memory block is shared by all cores. Such platforms accommodate popular parallel programming models such as POSIX threads and OpenMP. However with the growing number of cores in modern manycore embedded architectures, they present a bottleneck related to their centralized memory accesses. This paper proposes a solution tailored for an efficient execution of applications defined with shared-memory programming models onto on-chip distributed-memory multicore architectures. It shows how performance, area and energy consumption are significantly improved thanks to the scalability of these architectures. This is illustrated in an open-source realistic design framework, including tools from ASIC to microkernel.

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Scalability and programmability are important issues in large homogeneous MPSoCs. Such architectures often rely on explicit message-passing among processors, each of which possessing a local private memory. This paper presents a low-overhead hardware/software distributed shared memory approach that makes such architectures multithreading-capable. The proposed solution is implemented into an open-source message-passing MPSoC through developing a POSIX-like thread API, which shows excellent scalability using application kernels used for benchmarking in shared-memory systems. This approach efficiently draws strengths from the on-chip distributed private memory that opens the way to exposing the multithreading programmability/capabilities of that component as a general-purpose accelerator.

Semi-custom design flows are a key factor for the rapid growth of integrated circuits and systems. They lower design complexity through the use of pre-designed and pre-characterized functional components called standard cells, instead of assuming that designers have to draw, place and connect each transistor. In this way, modeling of complex systems is easier. As CMOS technologies evolve into deep sub micron nodes, asynchronous techniques gain relevance in the research community, due to their ability to cope with problems that are hard to solve with the synchronous paradigm. However, several specific components required in asynchronous designs are not available in commercial standard cell libraries, which constrains asynchronous design to use approaches close to full-custom ones. This limits modularity and increases design complexity. Thus, one of the possibilities for enabling further advance of the asynchronous paradigm is the availability of asynchronous standard cell libraries. Albeit industrial tools provide reasonable support to asynchronous standard cells physical design, the characterization of these cells using standard tools is usually quite laborious. This work proposes the Library Characterization Environment (LiChEn), an open source tool applicable to automatically characterize typical asynchronous standard cells. The tool managed to successfully characterize a standard cell library with over five hundred asynchronous components.

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

Message-passing is an increasingly popular design style for MPSoCs that usually results in systems that perform better compared to external shared-memory designs performance and power-wise, this because of much decreased data transfers with external memory. This scheme relies on explicit communications between processing tasks that participate in the application. Contrarily to shared-memory multiprocessors, tasks usually get assigned to processors at design-time. In order to cope with transient performance losses originating from various phenomena such as increased processing workload or peak traffic in the communication subsystem, various adaptation mechanisms based on task migration have been proposed in the literature. As Message-passing systems usually use PE-private memory architecture, these mechanisms imply migrating application code from processor to processor, which incurs penalty in performance and power consumption. This paper proposes a local shared-memory strategy in which processors execute code hosted in a remote processor.

This article explores the use of virtualization to enable mechanisms like task migration and dynamic mapping in heterogeneous MPSoCs, thereby targeting the design of systems capable of adapt their behavior to time-changing workloads. Because tasks may have to be mapped to target processors with different instruction set architectures, we propose the use of Low Level Virtual Machine (LLVM) to postcompile the tasks at runtime depending on their target processor. A novel dynamic mapping heuristic is also proposed, aiming to exploit the advantages of specialized processors while taking into account the overheads imposed by virtualization. Extensive experimental work at different levels of abstraction---FPGA prototype, RTL and system-level simulation---is presented to evaluate the proposed techniques.

The yield of homogeneous network-on-chip based multi-processor chips can be improved with the addition of spare tiles. However, the impact of this reliability approach on the chip energy consumption is not documented. For instance, in a homogeneous MPSoC, application tasks can be placed onto any tile of a defect-free chip. On the other hand, a chip with defective tile needs a special task placement, where the faulty tile is avoided. This paper presents a task placement tool and the evaluation of energy consumption of homogeneous NoC-based MPSoCs with spare tiles. Results show NoC energy consumption overhead ranging from 1 to 10% when considering up to three faults randomly distributed over the tiles of a 3×4 mesh network. The results also indicate that faults on the central tiles typically have more impact on energy overhead.

To cope with the dynamic workload of actual NoC-based MPSoCs, dynamic mechanisms are required to guarantee the application requirements. Application mapping may drastically influence the system performance and the energy consumption, which can be crucial to the success (or failure) of a product, even more for battery-powered embedded systems. In this context, the current work presents an energy-aware dynamic task mapping heuristic, which was evaluated in a real NoC-based MPSoC platform. Results show that the proposed heuristic may reduces up to 22.8% of the communication energy consumption compared to other dynamic mapping heuristics.

The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.