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M. Chastain

dblp:22/1696 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 67% Operating systems · 33%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor		 0.011988
The convex C240 architecture · SC 1988
Parallel and multicore computing › multiprocessor system
tightly-coupled multiprocessor		 0.011988
The convex C240 architecture · SC 1988
Compilers and program optimization › parallelization
automatic parallelization		 0.011988
The convex C240 architecture · SC 1988
Compilers and program optimization
vectorization		 0.011988
The convex C240 architecture · SC 1988

Methods — techniques the papers use, named apart from their topics

automatic vectorization · 0.0automatic parallelization · 0.0
YearPublicationVenuePosition
1988 The convex C240 architecture
abstract
A description is given of the C240, a tightly coupled, shared memory, parallel multiprocessor that supports up to 40-ns ECL/CMOS Cray-like processors. It is managed by a fully semaphored Unix operating system and can support up to 4 Gb of directly addressable physical memory. Convex proprietary compiler technology provides automatic vectorization and parallelization for Fortran, C and Ada. The allocation of parallel threads to physical processors is managed by ASAP (automatic self-allocating processors), which dynamically allocates and deallocates parallel threads to the processors.>
M. Chastain, G. Gostin, James E. Mankovich, Steven J. Wallach
 SC1