VLDB 2026 Research / reviewers in the wild / expert
Mark R. Hartoog
dblp:22/2121
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1997
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 85% Processor architecture and microarchitecture · 15% | |
| Software engineering, system software, and programming languages
1 paper |
Runtime systems and virtual machines · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware/software co-design |
0.0 | 1 | 1997 | Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign · DAC 1997 |
Runtime systems and virtual machines › virtual machine implementation
instruction set simulation |
0.0 | 1 | 1997 | Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign · DAC 1997 |
Processor architecture and microarchitecture › special-purpose processor
digital signal processor |
0.0 | 1 | 1997 | Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign · DAC 1997 |
Electronic design automation
physical design |
0.0 | 1 | 1986 | Analysis of placement procedures for VLSI standard cell layout · DAC 1986 |
Electronic design automation › physical design
placement |
0.0 | 1 | 1986 | Analysis of placement procedures for VLSI standard cell layout · DAC 1986 |
Electronic design automation › physical design › placement › cell placement
standard cell placement |
0.0 | 1 | 1986 | Analysis of placement procedures for VLSI standard cell layout · DAC 1986 |
Methods — techniques the papers use, named apart from their topics
nML processor description language · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1997 | Generation of Software Tools from Processor Descriptions for Hardware/Software CodesignabstractAn experimental set of tools that generate instruction set simulators,assemblers, and disassemblers from a single description wasdeveloped to test if retargetable development tools would work forcommercial DSP processors and microprocessors. The processorinstruction set was described using a language called nML. TheTMS320C50 DSP processor and the ARM7 microprocessor weremodeled in nML. The resulting instruction set models executeabout 25,000 instructions per second, and compiled instruction setsimulation models execute about 150,000 instructions per second.The viability of this approach and the deficiencies of nML are discussed. Mark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai, Douglas D. Dunlop, Ed Harcourt, Neeti Khullar |
DAC | 1 |
| 1986 | Analysis of placement procedures for VLSI standard cell layout
Mark R. Hartoog |
DAC | 1 |