In this paper, we study the propagation of slew dependent bounding signals and the corresponding slew problem in static timing analysis. The selection of slew from the latest arriving signal, a commonly used strategy, may violate the rule of monotonic delay. Several methods for generating bounding signals to overcome this difficulty are described. The accuracy and monotonicity of each method is analyzed. These methods can be easily implemented in a static timer to improve the accuracy.

IDL is a hardware design language in use in the VLSI environment. It incorporates a significant number of high-level features such as groups, subroutines, and labels and is particularly well adapted to dealing with parallelism at the hardware level. In addition to being human intelligible (and therefore appropriate as a documentation medium), IDL code can be used to generate 2-level logic which, under the IDL system, can be manipulated in a number of ways, including product term factoring and minimization, feedback minimization, partitioning, merging, and verification. The IDL system contains several simulators that are driven by IDL code. The most common embodiment of IDL output in hardware is a PLA.

A simple procedure to produce a minimum length test set for a parity network is presented. If M is the largest fan in of any EX-OR gate element in the tree, 2M test patterns are chosen by considering only 2M test sequences, of length 2M, assigned to each signal line.

Programmable logic arrays (PLA's) are the logic implementation vehicle for many applications. Due to their regular structure, one is able to model and analyze many more of the likely physical faults than the conventional stuck faults considered for random combinational logic implementations. We investigate shorts between the lines and crosspoint defects (spurious absence or presence), as well as stuck faults in a PLA. It is shown that a complete crosspoint test set also detects most of all faults analyzed. The crosspoint-oriented test set is compact, easy to generate, and technology-invariant. For the test generation, the regularity of the PLA structure is utilized for ease of computation and for test set optimality. Groups of crosspoint defects are sensitized simultaneously. For each such fault group, a test configuration which contains the totality of the tests for the faults under consideration is efficiently generated. When the configuration is empty, there exists no test that detects the particular group of faults. A covering set of tests is then selected from the configuration. Our test generation method (TPLA) uses two basic and effective heuristics; they are the initial word ordering for processing and the use of look-ahead merit function whenever there is a free choice of values in a test input variables.

A theorem is presented that simplifies the computations necessary for complementing a Boolean function.

In this short note, the realization of an arbitrary switching function by an interconnection of threshold and parity elements is considered. Using several criteria, it is shown that parity functions and threshold functions are " opposites." This dis- similarity between threshold and parity elements coupled with the useful physical properties of parity elements indicates that a realization employing the two types of modules should be of interest. Since the modules realizing parity functions are identical, mass production can be employed to reduce the cost of realization. A particular two- level configuration of threshold and parity elements is discussed. The first level consists of parity elements and the second level consists of a single threshold element. It is shown that any switching function can be realized with the proposed structure. An optimal procedure for minimizing the number of parity elements in the realization is given. Furthermore, a suboptimal procedure which is much simpler than the optimal one is also proposed.

Abstract—In this note, a class of switching functions, called threshold-product functions, whose definition is analogous to that of threshold functions (which will be called threshold-sum functions), is studied in detail. It is shown that both threshold functions and parity functions are special cases of threshold-product functions. A simple and economical threshold-logic realization method is established for threshold-product functions. This economical realization method is based on constrained solutions for threshold-product functions. A systematic technique for finding a constrained solution for a threshold-product function is obtained, and this technique can be employed for testing whether a switching function is a threshold-product function as well. When the number of variables in a switching function is not large, say no more than 6, a simpler method for the above purposes is found. Furthermore, a threshold-logic realization method which yields a minimal realization for certain threshold-product functions is obtained.