The PyTorch programming interface enables efficient deployment of machine learning models, leveraging the parallelism offered by GPU architectures. In this study, we present the integration of the PyTorch framework with a compiler and runtime ecosystem . Our aim is to demonstrate the ability to deploy PyTorch-based models on FPGA-based SoC platforms, without requiring users to possess prior FPGA-based design experience. The proposed PyTorch model transformation approach expands the range of hardware architectures that PyTorch developers can target, enabling them to take advantage of the energy-efficient execution provided by heterogeneous computing systems. Our experiments involve compiling and executing real-life applications on heterogeneous SoC configurations emulated on the Xilinx Zynq Ultrascale+ ZCU102 system. We showcase our ability to deploy three distinct PyTorch applications, encompassing object detection, visual geometry group (VGG), and speech classification, using the integrated compiler and runtime system without loss of model accuracy. Furthermore, we extend our analysis by evaluating dynamically arriving workload scenarios, consisting of a mix of PyTorch models and non-PyTorch-based applications. Through these experiments, we vary the hardware composition and scheduling heuristics. Our findings indicate that when PyTorch-based applications coexist with unrelated applications, our integrated scheduler fairly dispatches tasks to the FPGA platform’s accelerator and CPU cores, without compromising the target throughput for each application.

Look-Up Table (LUT) implementation of transcendental functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. MultiPartite table method (MP) can circumvent the area problem by breaking up the implementation into multiple smaller LUTs. However, even these smaller LUTs may be big in high accuracy MP designs. Lossless LUT compression can be applied to one or more of these LUTs to further improve area and even timing in some cases. The state-of-the-art 2T-TIV and 3T-TIV methods decompose the Table of Initial Values (TIV) of MP into a table of pivots and tables of differences from the pivots. Our technique, which we call Fully Random Access differential LUT (FR-dLUT), instead uses differences of consecutive elements and results in a smaller range of differences. We also propose a variant of FR-dLUT with variable length coding (Huffman) called FR-dLUT-VL, which introduces don't cares into the difference tables and lets logic synthesis optimize them out. We implemented Verilog generators of MP for sine and exponential, where TIV is a conventional LUT as well as 2T-TIV, 3T-TIV, FR-dLUT, and FR-dLUT-VL. We synthesized the generated designs on FPGA and found that our techniques produce around 10% improvement in area and timing beyond the state-of-the-art in large bit widths.

During the process of implementing a parameterized hardware IP generator for an image fusion algorithm, we had a chance to test various tools and techniques such as HLS, pipelining, and PCIe logic/software porting, which we developed in a previous design project. Image fusion combines two or more images through a color transformation process. Depending on the application, different fps and/or resolution may be needed. Yet the specifics of the image-processing algorithm may frequently change causing redesign. If the target platform is FPGA, usually rapid yet optimized hardware implementation is required. All these requirements cannot be met only by HLS. Clever approaches in terms of architectural techniques such as unorthodox ways of pipelining, RTL coding, and creative ways of porting interface logic/software allowed us to meet the requirements outlined above. With all these in our arsenal, we were able to get 3 versions of the algorithm (with different fps and/or resolution) running on Cyclone IV and Arria 10 FPGAs in a fairly short amount of time. This paper explains the image fusion algorithm, our hardware architecture as well as our specific flow for rapid implementation of it.

This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small look-up tables, they match well with the hardware resources of an FPGA. The article then studies whether the division by the product of two constants is better implemented as two successive dividers or as one atomic divider. It also considers the case when only a quotient or only a remainder is needed. Finally, it addresses the correct rounding of the division of a floating-point number by a small integer constant. All these solutions, and the previous state-of-the-art, are compared in terms of timing, area, and area-timing product. In general, the relevance domains of the various techniques are different on FPGA and on ASIC.

Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of this problem, where the divisor is small and the circuit outputs a quotient and remainder. We propose a fast (low-latency) yet area-efficient combinational circuit topology, which we call Binary Tree based Constant Division (BTCD). BTCD uses a collection of small LUTs wired to each other to form a binary tree. The circuit also has bunch of adders, whose latencies are almost hidden as they operate in parallel with the binary tree. We wrote RTL code generators for BTCD and two previous works in the literature, then generated circuits for dividends of up to 128 bits and divisors of 3, 5, 11, and 23. We synthesized the generated RTL designs using a commercial ASIC synthesis tool. BTCD strikes a good balance between timing (latency) and area. It is up to 3.3 times better in Area-Timing Product (ATP) compared to the best alternative. ATP has a good correlation with energy consumption.

Biomedical signals (BSs), which give information about the normal condition and also the inherent irregularities of our body, are expected to have non-stationary character due to the time-varying behavior of physiological systems. The Fourier transform and the short time Fourier transform are the widely used frequency and time-frequency analysis methods for extracting information from BSs with fixed frequency and time-frequency resolution respectively. However, in order to derive relevant information from non-stationary BSs, an appropriate analysis method which exhibits adjustable time-frequency resolution is needed. The wavelet transform (WT) can be used as a mathematical microscope in which the time-frequency resolution can be adjusted according to the different parts of the signal. The discrete wavelet transform (DWT) is a fast and discretized implementation for classical WT. Due to the aliasing, lack of directionality and shift-variance disadvantages, the DWT exhibits limited performance in the process of BSs. In literature, an improved version of the DWT, which is named as Dual Tree Complex Wavelet Transform (DTCWT), is employed in the analysis of BSs with great success. In this study, considering the improvements in embedded system technology and the needs for wavelet based real-time feature extraction or de-noising systems in portable medical devices, the DTCWT is implemented as a sub-system in field programmable gate arrays. In proposed hardware architecture, for every data input-channel, DTCWT is implemented by using only one adder and one multiplier. Additionally, considering the multi-channel outputs of biomedical data acquisition systems, this architecture is designed with the capability of running in parallel for N channels.

Finding the value and/or index of the maximum (or minimum) element of a set of$n$numbers (each with$k$-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder (or minimum-finder) circuit topologies, which are parallel. We wrote circuit generators at hardware description language level for our topologies and previous works. Then we synthesized these circuits for 20 different$(n, k)$cases (with values up to 64) and compared their efficiency in timing (latency), area, and energy. The timing complexity of our fastest topology is O(log$n$+ log$k$), whereas the fastest in the literature is O(log$n$log$k$). The synthesis results showed that our fastest topology is 1.2-2.2 times (1.6 times on the average) faster than the state-of-the-art. In this paper, we argue that a more fair metric of area efficiency is area-timing product. In terms of ATP, our proposed topologies are better than the state-of-the-art in 19 out of the 20 cases. In terms of energy (i.e., power-timing product, abbreviated as PTP), we are better in 11 cases out of 20.

Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) circuits to carry out this operation. We propose a fast circuit topology called Array-Based maximum finder (AB) to determine both value and address of the maximum element within an n-element set of k-bit binary numbers. AB is based on carrying out all of the required comparisons in parallel and then simultaneously computing the address as well as the value of the maximum element. This approach ends up with only one comparator on the critical path, followed by some selection logic. The time complexity of the proposed architecture is O(log2n + log2k) whereas the area complexity is O(n2k). We developed RTL code generators for AB as well as its competitors. These generators are scalable to any value of n and k. We applied a standard-cell based iterative synthesis flow that finds the optimum time constraint through binary search. The synthesis results showed that AB is 1.2-2.1 times (1.6 times on the average) faster than the state-of-the-art.

Dynamic Partial Reconfiguration (DPR) of Xilinx FPGAs in cases where there is significant logic difference between subsequent configurations is made possible by Xilinx module-based PR flow. Xilinx supports this flow only for high-end FPGAs and requires paid license, without which Xilinx PlanAhead software disables the related knobs and features. This poster presents a unique methodology (called DPR-LD) that enables DPR of low-end and high-end Xilinx FPGAs and requires no paid license. DPR-LD stands for DPR for Large Differences. DPR-LD uses the free Xilinx difference-based bit file generation software (bitgen), which normally is meant only for small differences between subsequent configurations. DPR-LD can be realized through either FPGA Editor or PlanAhead. Our FPGA Editor flow requires several physical constraints to ensure contention-free implementation of static and dynamic modules. We use implementation, floorplanning, and placement constraints to partition the design into several physical regions (one per module) for mapping, packing, placement, and routing. In order to avoid routing of a module to cross over another module, "fortress block"s are used to isolate the modules from each other. However, fortress blocks lead to wasted FPGA resources. On the other hand, in our PlanAhead flow, the physical constraints are entered via a GUI, and the corresponding actual physical constraints are generated automatically and without wasting FPGA resources. To evaluate the two approaches, a proof-of-concept application with a single dynamic region was implemented using both flows. In addition, a multiple dynamic region design was implemented with our PlanAhead flow.

This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high throughput buses. We first propose fast/novel circuits for the fundamental problem of finding the first m 1's in an n-bit vector (from the left or right), i.e., generalized m-select Priority Encoder (mPE). The obvious solution to mPE is cascading m regular (1-select) PEs. Our solutions, however, are based on parallel prefix networks, where the nodes are replaced by “saturated adder”s. We use mPE as a building block to construct an mRRA, which has single cycle latency and can arbitrate up to m requests per clock cycle. We took two arbiters from the literature, TC-PPA (1-select) and 3DP2S (2-select), and generalized them into mRRAs, which we call mTC-PPA and 3DPmS-RRA. We wrote fully parameterized HDL code generators. Logic synthesis results show that mTC-PPA and 3DPmS-RRA are up to 100% faster than the cascade solution and have up to 65% smaller Area-Timing Products (ATP). Comparing mTC-PPA and 3DPmS-RRA, 3DPmS-RRA circuits are slightly faster than mTC-PPA on the average. In terms of ATP, mTC-PPA is superior by far and can be as small as 30% of 3DPmS-RRA.

High energy physics experiments require on-the-fly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates to energy of the particle, while pulse occurrence times are needed for event reconstruction. Traditionally, these parameters have been extracted with the help of complete racks of dedicated electronics. Our FPGA design on a general-purpose DAQ card does real-time pulse detection and high-precision curve fitting. It greatly shrinks required equipment in terms of form factor, cost, power usage, and setup time. Unlike traditional systems, we can handle bursts of back-to-back pulses, pulses as narrow as 6 ns and at rates over 1M pulses per second. We have a novel scalable architecture that combines pipelining and parallelism. Moreover, the parallel part of the architecture uses loop pipelining in each of its interleaved identical parallel processors (IIPPs). An IIPP is a specialized CPU, which executes nested loops, with number of iterations that varies from pulse to pulse. IIPPs are fed data from a FIFO by a priority encoder based dispatcher. Number of IIPPs can be calculated to meet any pulse rate and average pulse width. The architecture is flexible enough to work with a variety of curve fitting algorithms.

Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is defect-aware even at the crosspoint level. Such logic mapping works with a defect map per each manufactured chip. The problem can be expressed as matching of two bipartite graphs; one for the logic to be implemented and other for the nanocrossbar. This article shows that the problem becomes a Bipartite SubGraph Isomorphism (BSGI) problem within sub-nanocrossbars free of stuck-closed faults. Our heuristic KNS-2DS is an iterative rough canonizer with approximately O(N2) complexity followed by an O(N3) matching algorithm. Canonization brings a partial or full order to graph nodes. It is normally used for solving the regular Graph Isomorphism (GI) problem, while we apply it to BSGI. KNS stands for K-Neighbor Sort and is used for initializing our main contribution 2-Dimensional-Sort (2DS). 2DS operates on the adjacency matrix of a bipartite graph. Radix-2 2DS solves the problem in the absence of stuck-closed faults. With the addition of Radix-3 and our novel Radix-2.5 sort, we solve problems that also have stuck-closed faults. We offer very short runtimes (due to canonization) compared to previous work and have success on all benchmarks. KNS-2DS is also novel from the perspective of BSGI problem as it is based on canonization but not on a search tree with backtracking.

This paper addresses the NP-complete problem of mapping a logic function on to a nanocrossbar with a known defect map. We first show that this problem can be transformed into a Bipartite SubGraph Isomorphism (BSGI) problem. Then we present our proposed KNS-2DS algorithm, which canonizes both graphs in N2time (N being the number of nodes) and then matches them in N3time in the worst case. KNS-2DS uses a K-Neighbor Sort (KNS) to initialize our main contribution 2D-Sort (2DS). 2DS is an iterative rough canonizer that lets a straightforward matching algorithm complete the job. Our algorithm offers very short run-times (due to canonization) compared to previous work and has success on all benchmarks. KNS-2DS is also novel from the perspective of the BSGI problem in the sense that it is based on canonization but not on a search tree with backtracking.

Autocircuit is a next-generation synthesis tool which makes fundamental contributions in high-level design. It accepts behavioral HDL input descriptions with multiple clock edges with no restrictions on where those edges may or may not be placed in relation to HDL operations or control constructs. It achieves this generality by novel representations and algorithms; its control and data-flow representations are called "raw-states" and "use-trees", respectively. AUTOCIRCUIT focuses on word-oriented synthesis and bypasses logic synthesis for word-oriented operators, registers, and muxes. It maps directly to physical datapath layout tools using a unique parameterized netlist representation in which net connections themselves have a parameterized size defined by an expression.

This paper presents a new technique for software pipelining using the Petri nets. Our technique called the Petri Net Pacemaker (PNP) can create near optimal pipelines with less algorithmic effort than other techniques. The pacemaker is a novel idea which exploits the behavior of Petri nets to model the problem of scheduling operations of a loop body for software pipelining.>

A multiprocessor architecture called ALMP, which specifically suits loop pipelining, is proposed. The processors in ALMP work like machines in an assembly line in a plant. An assembly line scheduling method (ALMap) has also been developed. ALMP enables processors to communicate with each other through memory modules that shift from processor to processor as if they are on a conveyor belt. The scheduling method is briefly described, and architectural issues are examined.>