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VLDB 2026 Research / reviewers in the wild / expert

Darin B. Johnson

dblp:22/3773 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 65% Memory systems · 22% Interconnection networks and networks-on-chip · 6%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › cache design
data cache design		 0.011992
Data path issues in a highly concurrent machine · ISCA 1992
Processor architecture and microarchitecture › microprocessor design › processor core design
datapath design		 0.011992
Data path issues in a highly concurrent machine · ISCA 1992
Processor architecture and microarchitecture › register file
register file organization		 0.011992
Data path issues in a highly concurrent machine · ISCA 1992
Parallel and multicore computing
concurrent system		 0.011992
Data path issues in a highly concurrent machine · MICRO 1992

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1992 Data path issues in a highly concurrent machine
abstract
It is desirable to achieve high read bandwidths for the processing elements of highly concurrent SISD computers, both while keeping the register and memory write bandwidths low, and while keeping the interconnection networks simple. Solutions to these problems are proposed, simulated, verified, and measured. New techniques called write elimination and write liberation are presented that also greatly reduce the complexity of the data cache. The elimination of addressable hardware registers is also achieved.
Augustus K. Uht, Darin B. Johnson
 ISCA2
1992 Data path issues in a highly concurrent machine
Augustus K. Uht, Darin B. Johnson
 MICRO2