José M. Fojo

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1ranked-venue papers

1as first author

0since 2021 · last 1975

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 77% Integrated circuit design · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation logic synthesis	0.0	1	1975	A Method for Reducing the Number of Input Variables to Synchronous Sequential Circuits · IEEE Trans. Computers 1975
Integrated circuit design › digital circuit design › sequential circuit design synchronous sequential circuits	0.0	1	1975	A Method for Reducing the Number of Input Variables to Synchronous Sequential Circuits · IEEE Trans. Computers 1975

Year	Publication	Venue	Position
1975	A Method for Reducing the Number of Input Variables to Synchronous Sequential Circuits José M. Fojo, Fernando D. Barreiro	IEEE Trans. Computers	1