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Daniel Englender

dblp:22/663 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 87% Processor architecture and microarchitecture · 13%
Network and information security
1 paper
Hardware security and side channels · 50% Cryptographic primitives and cryptanalysis · 50%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis › authenticated encryption
GCM
0.112006
Improving Cost, Performance, and Security of Memory Encryption and Authentication · ISCA 2006
Hardware security and side channels › memory integrity
memory authentication
0.112006
Improving Cost, Performance, and Security of Memory Encryption and Authentication · ISCA 2006
Memory systems › memory encryption
counter-mode encryption
0.112006
Improving Cost, Performance, and Security of Memory Encryption and Authentication · ISCA 2006
Memory systems
memory encryption
0.112006
Improving Cost, Performance, and Security of Memory Encryption and Authentication · ISCA 2006
Processor architecture and microarchitecture › hardware-assisted security
secure processor architecture
0.012006
Improving Cost, Performance, and Security of Memory Encryption and Authentication · ISCA 2006

Methods — techniques the papers use, named apart from their topics

split counters · 0.1GCM · 0.1
YearPublicationVenuePosition
2006 Improving Cost, Performance, and Security of Memory Encryption and Authentication
abstract
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encryption/authentication scheme. Our new split counters for counter-mode encryption simultaneously eliminate counter overflow problems and reduce per-block counter size, and we also dramatically improve authentication performance and security by using the Galois/counter mode of operation (GCM), which leverages counter-mode encryption to reduce authentication latency and overlap it with memory accesses. Our results indicate that the split-counter scheme has a negligible overhead even with a small (32KB) counter cache and using only eight counter bits per data block. The combined encryption/authentication scheme has an IPC overhead of 5% on average across SPEC CPU 2000 benchmarks, which is a significant improvement over the 20% overhead of existing encryption/authentication schemes
Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin
ISCA2