Cache memories dissipate a large portion of processors' power budget. On the other hand, due to unbalanced stress condition on their SRAMs, aging of cache memories is one of the most challenging reliability issues in modern processors. Therefore, power management and aging mitigation of these memories are mandatory in recent nanoscale technologies to achieve reliable and stable functionality of processor. Regarding the fact that the rate of Narrow-Width Values (NWVs) stored in data-caches memory is more than 80%, this work proposes an NWV-aware power consumption reduction and aging mitigation technique. In the proposed data-cache memory, the operating voltage of memory blocks which store the most significant bits of cache words is adjustable according to the rate of NWVs to reduce cache power consumption and aging rate. Our simulations show the proposed technique decreases the overall power dissipation of a 32KB cache memory by 44.20%, with 0.55% and 2.4% performance and area overheads, respectively. This technique prolongs the lifetime of the cache by up to 1.96x.

Power dissipation of on-chip cache memories contributes a large portion of a processor's power consumption. Therefore, power management of cache memories is crucial in modern processors. On the other hand, bias temperature instability (BTI) is one of the most serious reliability concerns in SRAM-based on-chip memories. The effect of BTI on SRAM-cell transistors is manifested as their threshold-voltage shift over stress duration, which decreases the robustness of these structures. This paper presents a power consumption-reduction technique for data-cache memories, based on a storage management considering narrow-width values (NWVs), which additionally mitigates the BTI rate on the most aging susceptible SRAM cells of data-cache memory, as well. In the proposed technique, the most significant bits of data-cache memory words are stored in SRAM blocks that operate with lower VDD, to achieve the decrease of the related power consumption and aging rate. This is shown to reduce leakage-current and dynamic current of data-cache memory by 37.6% and 22.1%, respectively, besides improving its lifetime by up to 2.25x, all with negligible performance and area overheads.

In this paper, we present an automatic parameter extraction method with the GA (Genetic Algorithm) for surface-potential-based MOSFET models such as HiSIM (Hiroshima-university STARC IGFET Model). The method employs a two-stage extraction procedure operating on different sets of model parameters. Experimental results demonstrate that extraction of 34 parameters can be completed within 23 hours with PC (AthlonXP 2500), although this would typically take a human expert several days.

The temperature-independence point (TIP) of the drain current for MOS transistors in a 0.1 /spl mu/m-scale pocket-implant technology is gate-length (L/sub g/) dependent and has different magnitudes for n-MOSFET and p-MOSFET. Circuits such as ring-oscillators have a TIP, lying between the values for nand pMOSFET. The circuit TIP Is close to the n-MOSFET TIP for long L/sub g/ and gets closer to the p-MOSFET TIP for short L/sub g/. The reason is the different temperature dependence of electron and hole mobility as a function of L/sub g/. Due to the high field effect, oscillation periods of ring-oscillators with short L/sub g/ hardly improve, when the supply voltage is raised beyond the TIP. Therefore, an advantageous supply-voltage (V/sub DD/) choice for pocket-implant technologies is near the TIP of circuits, allowing a favorable combination of short switching delay and minimized temperature dependence. By designing the V/sub th,p/ closer to V/sub th,n/, not only the low power dissipation, due to the reduction of the TIP, but also the suppressed TIP fluctuation can be realized.

Abstract — We propose a method of correlating circuit performance with technology fluctuations during the circuit-design phase. The method employs test circuits sensitive for technology fluctuations and a circuit simulation model which enables to interpret the correlation. We validate our proposal with a cascode-current-source test circuit and the driftdiffusion MOSFET model HiSIM. The chosen test circuit allows to separate intra-chip and inter-chip technology fluctuations and to correlate these fluctuations with circuit-performance fluctuations. One important result is that intra-chip fluctuations increase faster than inter-chip fluctuations with decreasing gate length. Quantitative modeling with HiSIM reveals random fluctuation of the effective gate length as the most likely origin for these findings. I.

An elevated central-channel doping with a depth similar to the S/D junctions is proposed as the best measure for simultaneously improving MOSFET device and high speed circuit performances as well as minimizing their fluctuations.We base our arguments on hydrodynamic device simulation, measured device data of vertical MOSFETs with a central delta-doped impurity profile and include experimental results on doping-profile fluctuations along the channel, which have not been available previously.

Concurrent engineering aims at integrating technology, device and circuit development in parallel. We will show here an example for an EEPROM development case, which has been realized with a transient circuit simulator. A precise unified EEPROM model was developed describing all characteristics with surface potentials dependent on technological parameters. This new exact model enabled us to realize all requested goals from the first wafer run.

A reliable method to determine the threshold voltage V/sub th/ for MOSFETs with gate length down to sub-0.1 /spl mu/m has been developed. The method determines V/sub th/ by linear extrapolation of the transconductance g/sub m/ to zero and is therefore named "GMLE method". 2D simulations were performed to extract the physical meaning of the method and to prove its reliability for different technologies. The results reveal that determined V/sub th/ values always meet the threshold condition, i.e. the onset of inversion layer build-up.

In this paper, we describe a complete MOSFET model developed for circuit simulation based on fully consistent physical concept. The model describes all transistor characteristics as a function of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. Contrary to the expectation, the results show that our semi-implicit model including the iteration procedures can even reduce the CPU time significantly in comparison with a conventional model similar to BSIM2 including short-channel effects. This is due to the consistent description of the model equations for all transistor characteristics, which results in more straightforward device equations, once the surface potentials have been computed.

Tsividis and Suyama (1994) have given benchmark circuits to assess model quality for analog applications. They are mainly based on the drain current quality check. We propose here benchmark circuits with respect to capacitances and charges. The most serious failure of existing models is related to the charge partitioning to the source and the drain side. The influence of the failure on real applications will be demonstrated.

The reliability of CAD is dependent on the accuracy of models implemented into circuit simulators. However, precise models such as based on 2D numerical modeling are time consuming. Therefore, simplified analytical models have been developed and widely used. A problem is that such existing models are not valid for advanced MOSFETs with sub-micron channel length due to applied simplifications. By introducing fitting parameters to describe each additional short-channel phenomenon, the consistency of the models is violated. As a result the calculation time for circuit simulation increases considerably. In this paper the authors present a newly developed MOSFET model which describes the transistor characteristics consistently without any nonphysical fitting parameters. Using this model the calculation time is reduced in comparison with the conventional model due to the consistent inclusion of short-channel effects and the diffusion contribution to the carrier transport.>

For deep submicron MOSFET's short-channel effects dominate the transistor characteristics. We present here a new analytical MOSFET model for circuit simulation which includes these effects. The model is based on the charge-sheet approximation including the drift and the diffusion contributions. Additionally the model includes the contribution of the lateral electric field explicitly. Therefore it enables the calculation of the transistor characteristics, i.e., the drain current and the channel conductance, for all channel lengths down to a quarter-micron with one parameter set with high accuracy. Due to the physically consistent treatment of the model, a drastic reduction in the number of model parameters has been realized.>