In this paper we present a low-power semi-passive RFID enabled temperature sensor developed for cold chain management (perishable items, such as: food, vaccines and pharmaceuticals). The system is compliant with the standard ISO15693 for identification purposes and uses proprietary commands for temperature logging. The temperature operation range is from -40°C to 85°C being accurate to ±0.5°C, over the whole range, while consuming an average of 8.4μW when active. Special focus is given on the design of the temperature acquisition sub-system which integrates the sensor and the current mode dual slope ADC converter.

The yield of homogeneous network-on-chip based multi-processor chips can be improved with the addition of spare tiles. However, the impact of this reliability approach on the chip energy consumption is not documented. For instance, in a homogeneous MPSoC, application tasks can be placed onto any tile of a defect-free chip. On the other hand, a chip with defective tile needs a special task placement, where the faulty tile is avoided. This paper presents a task placement tool and the evaluation of energy consumption of homogeneous NoC-based MPSoCs with spare tiles. Results show NoC energy consumption overhead ranging from 1 to 10% when considering up to three faults randomly distributed over the tiles of a 3×4 mesh network. The results also indicate that faults on the central tiles typically have more impact on energy overhead.

This work explores the concept of design diversity redundancy applied to mixed-signal (MS) circuits. Results from fault injection experiments show a very good ability of the system to tolerate double faults.

Programmable analog devices are susceptible to radiation effects. TID effects are a matter of concern due to the thickness of oxides in common analog technologies and can be mitigated by HBD techniques and shielding. SEEs may also disturb programmable analog devices, and system level techniques based on on-line error detection and self-correction may be applied by using the available programmable resources of the device.

In this paper, a fault tolerance technique is proposed for the protection of NoC interconnects. The technique is based on data splitting and retransmission, providing for high NoC-based SoC reliability. For error detection, the proposed approach splits the communication data into two parity encoded halves. For error correction, only the erroneous half is doubled and retransmitted. Compared to the use of a conventional Hamming Code, we show that, for medium to large NoCs, the approach proposed in this work is less silicon costly, leads to the design of faster fault-free routers and, for the majority of faults, presents no performance degradation at system level.

In this paper, we propose a method to detect crosstalk faults within and among channels of mesh NoCs, using a global test strategy that is based on a particular set of test paths and test packet. All test paths must be activated simultaneously without resource conflict. The test packet is built using Maximal Aggressor Fault (MAF) vectors. The test strategy is capable of detecting 100% of the considered faults. The test application time grows quadratically with the NoC increase, but can be drastically improved by means of two alternative approaches also proposed in the paper. Those local approaches are based on simultaneously testing multiple victims or NoC regions unlikely to aggress each other. The test time then grows linearly and shows a very modest derivative.

This embedded tutorial presents an overview of the issues related to the test, diagnosis and fault-tolerance of Networks-on-chip (NoCs). The main motivation is the increasing interest on NoC-based designs in academia and industry. This new design option is becoming an important trend because of its advantages on tackling the challenges of a complex SoC design. However, to become a real standard or an industrial reality, it is important that the issues related to its testing are also well understood and dominated. Initially, the challenges to test and diagnose faults in NoCs are presented. A NoC is basically made up of three main components: network interface, routers and communication channels. To start with the network interface and routers, many works presented the problem of NoC testing suggesting that a wide variety of standard DfT solutions can be used. However, a deeper evaluation of the approaches brought from board-level and chip-level testing, shows that much better results, in terms of silicon overhead, test time and diagnosability, can be obtained if test approaches specific for NoCs are used. Testing and diagnosis of NoC channels is also important. The huge number of interconnects allied to the shrinking of the chip dimensions make the NoC prone to a growing number of interconnect faults. The capability of detecting interconnect faults in NoC-based SoCs is mandatory for yield improvement. Moreover, fault diagnosis of NoC interconnect links can help fault tolerance approaches to mitigate the faults and to maintain the network service. The most influent NoC test and diagnosis strategies are presented and comparatively discussed in this tutorial. In fact, the correctness of the on-chip network behavior is a feature that must be ensured, not only in test mode, but also during the mission of the system. In mission mode, all system communication is implemented through the NoC and designers assume a certain Quality of Service (QoS) level according to specific design techniques. However, current technologies are becoming quite sensitive to noise and cosmic particles that can cause transient faults. Thus, it is important to ensure that the NoC service is not compromised by those faults. This way, fault tolerance techniques for the communication infrastructure must be considered when designing a NoC-based system. Various techniques to detect and recover from transient and permanent faults are discussed in this embedded tutorial. For the last years a number of testing and fault tolerance approaches have been proposed for NoCs. Although this is a relatively new topic, current research covers already a considerable spectrum and its analysis at this point can help to summarize the scientific and technological advances made so far and to identify the open issues that still need to be tackled.

We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for the faulty links. Experimental results show that alternative fault-free paths are found by the dynamic routing for 95% of the diagnosed faults (stuck-at and pairwise shorts within a single link or between any two links).

This work proposes a simple, efficient and easy-to-use test circuit for evaluating and validating any set of logic gates in terms of functionality, performance, power consumption and impact in operation of sub-nanometer physical effects.

We propose a method to diagnose interconnect short-circuit faults in mesh 7oCs. The fault model comprises all shorts between any two wires of a defined 7oC neighborhood. Test sequences are applied in 7oC functional mode. Experimental results show that 93% of the interconnect shorts can be diagnosed.

In this work we analyze four techniques to protect a cryptographic core, which can be combined to allow for several implementations with different area overheads and protection levels. Experimental results show their efficiency in protecting the core against fault attacks, while being flexible enough to leave other design aspects to be explored by the core provider.

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.

An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.

This paper presents new DfT modules required to use networks-on-chip as test access mechanism. The paper demonstrates that the proposed DfT modules can be also implemented on top of low cost networks-on-chip, i.e. networks without complex services. The DfT modules, which consist of test wrappers and test pin interfaces, are designed such that both the tester and CUTs transport test data unaware of the network. The DfT modules was analysed in terms of silicon area and test time, considering different network and test configurations.

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Æthereal NoC. The results show the impact of of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM.

Current hardware design flows include test pattern generation as a single step to be performed only after logical synthesis. However, early generation of few high level test patterns can provide higher test quality and reduce ATPG effort. In this work, the authors apply a software engineering technique for control flow based path testing, to extract test vectors from the behavioral HDL description of digital circuits. The authors show how one can adapt this software testing approach to test hardware devices. Experimental results show that combining high level generated test vectors with gate level ATPG can improve test quality, either increasing fault coverage and/or reducing test set size

In this work a strategy for testing analog networks, known as transient response analysis method, is applied to test the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs). In this method the circuit under test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Different functions available in the component programming library are studied and a choice is made in order to obtain the best results in terms of sensitivity and test coverage. A functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted and the relationship between these parameters and CAB component deviations is investigated, therefore allowing to estimate the fault coverage and test application time of the proposed functional test method

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increase in the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the test access mechanism. Experimental results are based on ITC'02 benchmarks and on two open core processors, compliant with MIPS and SPARC instruction sets. The results show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time without additional cost in area and pins.

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models

The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.

The problem of testing the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs) is addressed in This work. The considered fault model comprises deviations in the nominal values of CAB programmable capacitors, deviations in the programmable gains of CAB input amplifiers and stuck-on/stuck-open faults in CAB switches. The problem of test stimuli generation is solved, in a first approach, by using the oscillation test strategy (OTS), which is associated to a test response analysis external to the device under test. In a second approach, a built-in self-test (BIST) scheme is proposed by associating to the OTS an output response analyzer (ORA) built using the internal FPAA resources. Both approaches are validated using the ispPAC10 FPAA from the Lattice Semiconductor Corporation. In the paper, the approaches are compared in terms of fault coverage, test application time and required external hardware resources for testing. Experimental results show that a good compromise of these aspects can be found by taking the best of each approach.

The use of the oscillation test strategy to test configurable analog blocks of field programmable analog arrays (FPAAs) has been proposed previously, solving the complex problem of test stimuli generation. An improvement to that technique is presented in this paper, using the resources of the FPAA to build an output response analyzer. This new approach offers a full built-in self-test scheme with no area overhead and requiring a low cost automatic test equipment. Experiments show the efficiency of the approach in detecting parametric faults of the tested components.

Networks-on-chip are likely to become the main communication platform of systems-on-chip. To cope with the growing complexity of the test of such systems, the authors propose the reuse of the on-chip network as a test access mechanism to the cores embedded into systems that use this communication platform. An algorithm exploiting the network characteristics to minimize test time is presented. Then, the reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results for the ITC'02 SOC Test Benchmarks show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider power consumption during test, while minimizing the system testing time. Experimental results with the ITC'02 SoC benchmarks show that although power constraints can preclude the full exploration of the network parallelism, this platform is still a powerful mechanism for the system test time reduction at a very low cost.

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the consideration of different optimization factors (area, ping and test time) during the global TAM and test schedule definition. This expansion of concerns makes possible an efficient yet fine-grained search in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test design.

This work presents a design for test method for continuous time active filters of any order, using the IEEE 1149.4 as its backbone structure. The method relies on the synthesis of filter transfer functions using partial fraction extraction. Transfer functions are built from 1/sup st/ order blocks connected via the available standard infrastructure. Under this approach, structural test can be carried out using simple test vectors, which are disclosed according to a fault simulation process.

The use of analog VLSI technology on ordinary but complex electronic products has in the test one of its last frontiers. The design for testability paradigm should allow the test plan implementation early in the design cycle. However, in a successful test strategy, fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade, etc. This way adequate fault models must be established. This paper shows the suitability and the straightforward consequences on testing of complex analog circuits when using OpAmp functional fault macromodels. Due to the lack of fault models, suitable for operational amplifiers fault simulation, we propose methodology for functional fault modeling and a method for test pattern generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The method is used to detect OpAmp faults in a pulse width modulator. The obtained results show that the proposed method is able to verify high level OpAmp requirements, such as open loop gain, slew-rate and CMMR, with good compromise between fault modeling and the analog circuit simulation complexity.

This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation, validated by simulation results.

The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8/sup th/ order analog linear filter is used as an application example. The required modifications in the circuit are presented with the results in terms of area overhead and fault coverage.

This work proposes a new BIST scheme for 2nd order Butterworth, Chebyshev and Bessel filter approximations, using the transient analysis of simple input test vectors. A functional approach for fault modeling in 2nd order filters is presented and the transient response method is used for fault detection. The approach considers the filter as a 2nd order dynamic system where /spl omega/c and Qp deviations are faults to be detected. The peak time is the observed parameter that is evaluated in order to verify the filter correctness. The obtained results are very promising since all of /spl omega/c and Qp deviations as well as 100% of passive components are detected for this BIST scheme.

A design methodology for on-line testing analog linear fully differential (FD) circuits is presented in this work. The test strategy is based on concurrently monitoring via an analog checker the common mode (Chi) at the inputs of all amplifiers, The totally self-checking (TSC) goal is achieved for linear FD implementations provided that the checker CM threshold is small enough with respect to the specified margins of erroneous behavior in the circuit outputs. The design methodology is illustrated for a switched-capacitor biquadratic filter and the self-checking properties evaluated for a hard/soft-fault model. A large checker threshold of 100 mV of CM is chosen since the filter implementation does not minimize nonidealities (e.g., amplifier offsets or clock feedthrough) which result in significant CM components. The circuit outputs are accepted to deviate within a 10% band. With the implemented checker, the TSC goal is not achieved for some faults in narrow regions of the frequency band. For the worst case, a hard fault which results in a 31% deviation is undetected in only a narrow band of approximately 310 Hz. The circuit can be made TSC with a checker threshold of 40 mV and an accepted output deviation of 15%. This is, however, more demanding on the checker (which currently takes less than 3% of the total area and about 7.6% of the total power) and requires an improved filter implementation to reduce CM components. Our solution consists of relaxing a bit the TSC property of the functional block and applying a periodical off-line test to make the checker strongly code disjoint (SCD). This is easy to implement since an off-line test is also required for the checker. The checker outputs a double-rail error indication which ensures compatibility with digital checkers and makes the design of self-checking mixed signal circuits straightforward. The circuit-level mixed-signal approach is extended to the board level by means of the IEEE Std. 1149.1 digital test bus.

This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behaviour in a first step, and comparing this behaviour against the output of the circuit under test in a second step. Considering the same basic structure, the diagnosis method consists on injecting probable faults in a mathematical model of the circuit and later comparing its output with the output of the real faulty circuit. This method has been successfully applied to a case study, a biquad filter. Component soft, large, and hard deviations, and faults in operational amplifiers were considered. The results obtained from practical experiments with this analog circuit are discussed in the paper.

As next generation chips embedding MEMS appear, fault-based and defect-oriented tests for MEMS parts become important for cost-effective production testing. This paper presents realistic fault modeling and simulation techniques for suspended thermal MEMS, an already successful domain of application.

A new approach for the on-line testing of operational amplifiers embedded into analog and mixed-signal circuits is presented in this paper. A built-in detector is used for providing an on-line test signal, which is suitable for concurrent error detection in operational amplifiers. The fault detection strategy is based on monitoring via an analog checker the normal output/input and the on-line signal of operational amplifiers. In this context, the circuitry associated with a self-checking operational amplifier is presented. In order to evaluate the fault coverage and the performance degradation in the resulting operational amplifier, extensive simulations are performed considering catastrophic faults.

In this work a Computer-Aided Testing (CAT) tool is proposed that brings a systematic way of dealing with testing problems in emerging microsystems. Experiments with case-studies illustrate the techniques and tools embedded in the CAT environment. Some of the open problems that shall be addressed in the near future as an extension to this work are also discussed.

The paper describes a fault tolerant system that is based on two replicas of a self checking module and on an error masking interface. The main contributions of this work rely on the fail safe/strongly fail safe design of the error masking interface, and on the analysis of the competitiveness of this fault tolerant scheme with respect to its reliability.

On-line temperature monitoring of safety-critical ICs and systems becomes more and more crucial because of downsizing of integrated circuits and of increased density due to advanced packaging. To prevent erroneous operation, temperature sensors should be placed on the critical spots, the outputs of which should be read by means of boundary scanned architectures or modified boundary scanned architectures in case of on-line monitoring.

This paper presents a novel multifunctional test structure called Analog BulLt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.

In this paper we propose a configuration for a VLSI analog sine wave generator with an appropriate frequency BIST. The generator is used for testing circuits that require sinusoidal input signals with a variable frequency as an input stimulus. The detectors indicate any deviation of the frequency input signal from the nominal value /spl plusmn//spl epsiv/. A sine wave generator and two different BISTs are proposed: the defection and translation (DandT) T-BIST approach and the frequency-counter BIST approach. Some experimental results are also presented.

The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code fails out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattern generator for off-line testing of the checkers is proposed.>

An approach to the test and diagnosis of fully dif-ferential analogue circuits is described in this paper. The test approach is based on o-line monitoring via an analogue BIST observer the inputs of the opera-tional ampliers in the circuit. The analogue BIST can detect both hard and soft faults. Diagnosis resolu-tion is improved by also monitoring the outputs of the operational ampliers. Faulty components can then be located and the actual defective value of a faulty pas-sive component determined. 1

The design of checkers suitable for concurrent error detection in analogue and mixed-signal circuits is addressed in this paper. These checkers can on-line test duplicated and fully differential analogue functional circuits and comply with existing digital self-checking parts. A test pattern generator for off-line testing of the checkers is proposed, which fully exercises their capability of signalling functional error occurrences.>

A methodology is presented that unifies the fault detection and fault diagnosis of boundary scan (BS) interconnects and logic clusters in partial boundary scan boards. The software implementing this methodology and some experimental results are also described.

In this paper the Boundary Scan technique and the Un@ed Built-In Self-Test scheme are combined in order to propose a strategy suitable for the manufacturing, the field testing and the concurrent error detection on integrated circuits and board interconnects. Such unification of the off-line and the on-line testing plays a major role in the design for broad testability of self-checking boards. This unified test strategy is primarily aimed at critical application designs: transportation systems, nuclear plants, etc.. ., which are the main targets. This architecture, oriented primarily towards the off-line test, provides efficient means of testing of circuits and board interconnects. The association of BIST and BS techniques leads to a significant reduction of the automatic test equipment complexity, due to lower memory requirements and weaker test time constraints. The other part of the tests necessary for circuits and boards is related to the on-line testing capability, a feature of great importance for systems where poor functioning can, for example, lead to a disaster. This is the case of railway, automotive and nuclear systems, where errors must be detected before they contaminate other units and at a point where basic repair is still possible. The self-checking circuit implementation, for making on-line testing possible, is based on the encoding of functional block outputs and on the verification of