Robert Suszynski

dblp:22/9088 · DBLP profile ↗
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10ranked-venue papers
1as first author
10since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 10 · 1 first-author · 10 since 2021
YearPublicationVenuePosition
2025 The Concept of Self-Adaptive Dynamic Reconfiguration in FPGA-Based DSP Systems
abstract
This article presents the concept of digital signal processing (DSP) systems implemented in FPGA (Field-Programmable Gate Array) devices, utilizing Dynamic Partial Reconfiguration (DPR) mechanisms. It describes hardware architectures that enable selective replacement of logic configuration fragments in real time. Applications of DPR are proposed for the implementation of Fast Fourier Transform (FFT), adaptive filtering, and sound signal synthesis, where the choice of algorithm and its parameters can be dynamically adjusted based on the quality requirements of the processed signal and hardware resource constraints. Additionally, the use of adaptive mechanisms, including artificial intelligence, is discussed as a means of supporting the configuration selection process based on quality test results such as Signal-to-Noise Ratio (SNR), latency, processing time and energy consumption. The article explores the potential of using evolutionary algorithms, large language models (LLMs), and reinforcement learning for the generation and optimization of hardware configurations. The integration of the hardware layer (Intel and Xilinx FPGA) with the software layer is also presented, using Tool Command Language (TCL) scripts and AI systems. Methods for evaluating the quality of DSP algorithm implementation are proposed. The presented solutions make it possible to build digital signal processing systems that automatically adapt their hardware architecture to improve signal processing quality while minimizing resource usage.
Lukasz Golka, Pawel Poczekajlo, Robert Suszynski
KES3
2025 Forth Language Extensions for DSP: Configurable FIFO and LIFO Structures
abstract
The article presents the concept and implementation of an extended Forth language model, dedicated to digital signal processing (DSP) tasks. The classical FORTH language has been enhanced with additional data structures, including FIFO_IN, FIFO_OUT, a temporary stack (TEMP), and two configurable generators (G1 and G2) with support for offsetting, automatic incrementing, looping, and data mirroring. The model was implemented in the MATLAB environment as a Forth interpreter capable of collecting instruction execution statistics. As part of the study, an autocorrelation algorithm was implemented in two variants: the classical (dual-stack) version and the extended version. The conducted experiments demonstrated that the extended variant significantly reduces the number of operations required to execute the same algorithm. The proposed model may serve as an intermediate stage prior to hardware implementation (e.g., on FPGA platforms).
Lukasz Golka, Robert Suszynski, Pawel Poczekajlo
KES2
2025 Monitoring the Efficiency of Automatic Screens Based on Computational Analysis of Wastewater Level Variations
abstract
The quantity of solid waste entering the sewage system is contingent on a number of factors, including the type of wastewater, the time of day and year, prevailing weather conditions, as well as the habits and awareness of users of the sewage infrastructure. In this regard, the water and sewerage company in Koszalin (northern Poland), where this study was conducted, initiated a long-term information campaign in 2019 under the slogan "Keep waste out of the sewer system". The objective of the campaign was to raise residents’ awareness of the detrimental consequences of improper use of the sewerage system, particularly in terms of the disposal of solid waste into the network that should not be there. This paper presents the findings of an investigation into alterations in the level of wastewater measured using an ultrasonic probe situated in front of automatic step gratings with a clearance width of 3 mm. The measurement data (comprising more than 186,000 records) were systematically recorded at a frequency of 10 seconds over a period of three weeks in the WinCC system of a municipal wastewater treatment facility. The number of grating engagements in each hour was then calculated based on the local minima of wastewater levels. Subsequent data analysis was conducted on a weekly basis, with a distinction made for each of the three independently operating screens. In the preliminary phase of the study, a hypothesis was formulated concerning the variations in the efficiency of the grilles, attributable to the duration since their most recent comprehensive overhaul. The results of the analysis confirmed the assumption of varying efficiency of pollutant separation, with screens displaying a higher degree of wear showing a lower number of engagements per hour, which may indicate a reduction in their efficiency. The findings of the study indicated that the implementation of an effective monitoring system to assess the efficiency of automatic screens used for the separation of solids from wastewater can be facilitated by the analysis of changes in the level of wastewater in front of the screens.
Piotr Maciolek, Robert Suszynski, Aneta Hapka, Karolina Napiórkowska
KES2
2024 Implementation of a universal replicable DSP core in FPGA devices for cascade audio signal processing applications
abstract
The article presents the concept of a universal DSP core, enabling the creation of systems compliant with various processing architectures, such as Single Instruction, Multiple Data - SIMD, Multiple Instruction, Multiple Data - MIMD. The aim was to facilitate a simpler and faster configuration and programming process for complex and more efficient signal processing systems, while minimizing the need for hardware description languages. The architecture and instruction set for the DSP core are described, allowing for simultaneous addressing of multiple operands in a single instruction. Unidirectional signal flows between cores are proposed, resulting in a reduction of connections and increased performance. The testing process and comparison of results with computations performed in Matlab are described. The paper points out future research directions, such as hardware optimization, increasing the number of cores, developing floating-point computations, and modular system construction. The proposed solutions can significantly impact the efficiency and flexibility of future signal processing systems.
Lukasz Golka, Pawel Poczekajlo, Robert Suszynski
KES3
2024 The concept of multicore computing and processing in a field-programmable gate array chip
abstract
The article concerns the issue of multicore processing and implementation. The topic is introduced considering the functional division of various architectures. Examples of large-scale multicore architectures (with 144 and 1024 computational cores) are also presented. The main goal of the authors is to present the concept of implementing a multicore architecture in a Field-programmable gate array (FPGA). An available solution of the Nios II processor from the Intel library in the Quartus environment is presented. Additionally, the authors discuss their own concept of a computational core, outlining key assumptions, advantages and disadvantages, as well as potential issues.
Pawel Poczekajlo, Lukasz Golka, Robert Suszynski, Patryk Widulinski
KES3
2024 Engineering energy measurement system and data analising for an electric elevator
abstract
The article discusses the possibilities of measuring electrical energy consumption using selected modules. Several IoT devices and typical installation modules (for electrical switchboards) are presented. The authors applied one of the modules (three-phase) to measure energy consumption by an elevator located in a public building. Weekly and daily charts (cumulative and with 10-minute measurement periods) are presented. The collected measurement data are analyzed. Based on the results, potential savings associated with the continuous operation of the elevator system (mainly at night) - lack of sleep/standby function are determined. It is estimated that potential reduction in electrical energy consumption by the elevator could be up to 18.5% (on a weekly basis).
Pawel Poczekajlo, Robert Suszynski, Andrzej Antosz
KES2
2023 An attempt at the possibility of using multi-output paraunitary filters for image processing for astrophotography trackers
abstract
The article deals with the issue of stabilizing the frame position of the shot in long time astrophotography. The authors described this issue from the point of view of guiding a telescope following of the sky, and also in terms of the possibility of supporting this process with digital signal processing using paraunitary filters. The procedure for obtaining a 2D paraunitary system from an initial (preset) filter is presented. An attempt is made to verify the data that can be obtained from individual outputs of paraunitary systems. Several example filters were shown and their operation was tested on a selected image of a real astronomical object from the telescope's guide camera. Based on the output images obtained (from three paraunit systems), the possibility of their further use in practice was evaluated.
Pawel Poczekajlo, Robert Suszynski
KES2
2023 The use of modern methods of virtualization and shared network functions to optimize the resources used
abstract
The article addresses the virtualization of network functions and services for sharing with local and national operators. Reference was made to services for campus units (universities), where integration of services is also important. Consideration was given to the possibility of expanding interuniversity cooperation in IT infrastructure and services. The authors were identified a number of important issues from the point of view of academics. Opportunities for development were demonstrated with an indication of the key advantages and disadvantages of virtualization. The focus was on optimization opportunities with particular attention to reducing personnel, hardware and energy costs, as well as security and redundancy issues. Conditions for a conceptual (prototype) workstation were discussed. Subsequent research steps were presented, including implementation testing and analysis of the required network infrastructure. All aspects take into account the possibility of collaboration between units (e.g., academic units) through the introduction of virtualization and shared services. The article provides an overview of the solutions, indicating advantages and disadvantages, and presents conceptual possibilities for the development and implementation of selected solutions.
Pawel Poczekajlo, Robert Suszynski, Andrzej Antosz
KES2
2021 Modern computing methods for digital signal processing engineering systems
abstract
In the paper, the design and implementation of DSP systems with the use of modern computing and data processing methods are presented. The parallel processing and pipeline implementation of calculations as well as a number of solutions in the field of modern processing techniques, such as genetic algorithms, are proposed. New possibilities and approach to designing and implementing DSP systems in the field of cloud computing are also discussed.
Pawel Poczekajlo, Robert Suszynski
KES2
2021 The latest developments in computer science and their impact on space exploration
abstract
In the paper, the important role of tools and distributed IT resources in the dynamic development of astrophysics, astronomy, and space exploration are discussed. New possibilities and approaches to conducting research in the field of astronomy and astrophysics with the use of cloud computing and advanced data visualization techniques are also presented. Finally, some examples of the use of digital sky survey databases in scientific research are shown.
Robert Suszynski, Pawel Poczekajlo
KES1