This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

Given the recent progress in the evolution of high-performance computing (HPC) technologies, the research in computational intelligence has entered a new era. In this paper, we present an HPC-based context-aware intelligent text recognition system (ITRS) that serves as the physical layer of machine reading. A parallel computing architecture is adopted that incorporates the HPC technologies with advances in neuromorphic computing models. The algorithm learns from what has been read and, based on the obtained knowledge, it forms anticipations of the word and sentence level context. The information processing flow of the ITRS imitates the function of the neocortex system. It incorporates large number of simple pattern detection modules with advanced information association layer to achieve perception and recognition. Such architecture provides robust performance to images with large noise. The implemented ITRS software is able to process about 16 to 20 scanned pages per second on the 500 trillion floating point operations per second (TFLOPS) Air Force Research Laboratory (AFRL)/Information Directorate (RI) Condor HPC after performance optimization.

Neural logic blocks (NLBs) enable the realization of biologically inspired reconfigurable hardware. Networks of NLBs can be trained to perform complex computations such as multilevel Boolean logic and optical character recognition (OCR) in an area- and energy-efficient manner. Recently, several groups have proposed perceptron-based NLB designs with thin-film memristor synapses. These designs are implemented using a static threshold activation function, limiting the set of learnable functions to be linearly separable. In this work, we propose two NLB designs-robust adaptive NLB (RANLB) and multithreshold NLB (MTNLB)-which overcome this limitation by allowing the effective activation function to be adapted during the training process. Consequently, both designs enable any logic function to be implemented in a single-layer NLB network. The proposed NLBs are designed, simulated, and trained to implement ISCAS-85 benchmark circuits, as well as OCR. The MTNLB achieves 90 percent improvement in the energy delay product (EDP) over lookup table (LUT)-based implementations of the ISCAS-85 benchmarks and up to a 99 percent improvement over a previous NLB implementation. As a compromise, the RANLB provides a smaller EDP improvement, but has an average training time of only ≈ 4 cycles for 4-input logic functions, compared to the MTNLBs ≈ 8-cycle average training time.

This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.

Memristor, the fourth passive circuit element, has attracted increased attention since it was rediscovered by HP Lab in 2008. Its distinctive characteristic to record the historic profile of the voltage/current creates a great potential for future neuromorphic computing system design. However, at the nano-scale, process variation control in the manufacturing of memristor devices is very difficult. The impact of process variations on a memristive system that relies on the continuous (analog) states of the memristors could be significant. We use TiO2-based memristor as an example to analyze the impact of geometry variations on the electrical properties. A simple algorithm was proposed to generate a large volume of geometry variation-aware three-dimensional device structures for Monte-Carlo simulations. A neuromorphic computing system based on memristor-based bidirectional synapse design is proposed as case study. We analyze and evaluate the robustness of the proposed system in pattern recognition based on massive Monte-Carlo simulations, after considering input defects and process variations.

As the technology scales down, the increased power density brings in significant system reliability issues. Therefore, the temperature monitoring and the induced power management become more and more critical. The thermal fluctuation effects of the recently discovered spintronic memristor make it a promising candidate as a temperature sensing device. In this paper, we carefully analyzed the thermal fluctuations of spintronic memristor and the corresponding design considerations. On top of it, we proposed a temperature sensing circuit design by combining spintronic memristor with the traditional CMOS current reference. Our simulation results show that the proposed design can provide high accuracy of temperature detection within a much smaller footprint compared to the traditional CMOS temperature sensor designs. As magnetic device scales down, the relatively high power consumption is expected to be reduced.

Memristors have been rediscovered recently and then gained increasing attentions. Their unique properties, such as high density, nonvolatility, and recording historic behavior of current (or voltage) profile, have inspired the creation of memristor-based neuromorphic computing architecture. Rather than the existing crossbar-based neuron network designs, we focus on memristor-based synapse and the corresponding training circuit to mimic the real biological system. In this paper, first, the basic synapse design is presented. On top of it, we will discuss the training sharing scheme and explore design implication on multi-synapse neuron system. Energy saving method such as self-training is also investigated.

The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal-oxide-semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.

The fourth passive circuit element, memristor, has attracted increased attentions since the first real device was discovered by HP Lab in 2008. Its distinctive characteristic to record the historic profile of the voltage/current through itself creates great potentials in future system design. However, as a nano-scale device, memristor is facing great challenge on process variation control in the manufacturing. In this work, we analyze the impact of the geometry variations on the electrical properties of both TiO2thin-film and spintronic memristors, including line edge roughness and thickness fluctuation. A simple algorithm was proposed to generate a large volume of geometry variation-aware three-dimensional device structures for Monte-Carlo simulations. Our simulation results show that due to the different physical mechanisms, TiO2thin-film memristor and spintronic memristor demonstrate very different electrical characteristics even when exposing them to the same excitations and under the same process variation conditions.

Resistive random access memory (ReRAM) has been demonstrated as a promising non-volatile memory technology with features such as high density, low power, good scalability, easy fabrication and compatibility to the existing CMOS technology. The conventional three-dimensional (3D) bipolar ReRAM design usually stacks up multiple memory layers that are separated by isolation layers, e.g. Spin-on-Glass (SOG). In this paper, we propose a new 3D bipolar ReRAM design with interleaved complimentary memory layers (3D-ICML) which can form a memory island without any isolation. The set of metal wires between two adjacent memory layers in vertical direction can be shared. 3D-ICML design can reduce fabrication complexity and increase memory density. Meanwhile, multiple memory cells interconnected horizontally and vertically can be accessed at the same time, which dramatically increases the memory bandwidth.

The emerging memristor devices have recently received increased attention since HP Lab reported the first TiO2-based memristive structure. As it is at nano-scale geometry size, the uniformity of memristor device is difficult to control due to the process variations in the fabrication process. The incurred design concerns in a memristor-based computing system, e.g, neuromorphic computing, can be very severe because the analog states of memristors are heavily utilized. Therefore, the understanding and quantitative characterization of the impact of process variations on the electrical properties of memristors become crucial for the corresponding VLSI designs. In this work, we examined the theoretical model of TiO2thin-film memristors and studied the relationships between the electrical parameters and the process variations of the devices. A statistical model based on a process-variation aware memristor device structure is extracted accordingly. Simulations show that our proposed model is 3 ~ 4 magnitude faster than the existing Monte-Carlo simulation method, with only ~ 2% accuracy degradation. A variable gain amplifier (VGA) is used as the case study to demonstrate the applications of our model in memristor-based circuit designs.

The United States Air Force Research Laboratory (AFRL) has been exploring the implementation of neurophysiological and psychological constructs to develop a hyper-parallel computing platform. This approach is termed neuromorphic computing. As part of that effort, the primary visual cortex (V1) has been modeled in high performance computing facility. The current columnar V1 model is being expanded to include binocular disparity and motion perception. Additionally, V2 thick and pale stripes are being added to produce a V1/V2 stereomotion and form perception system. Both the V1 and V2 models are based upon structures approximating neocortical minicolumns and functional columns. The neuromorphic strategies employed include columnar organization, integrate-and-fire neurons, temporal coding, point attraction recurrent networks, Reichardt detectors and “confabulation” networks. The interest is driven by the value of applications which can make use of highly parallel architectures we expect to see surpassing one thousand cores per die in the next few years. A central question we seek to answer is what the architecture of hyper-parallel machines should be. We also seek to understand computational methods akin to how a brain deals with sensation, perception, memory, attention decision-making.

As conventional CMOS technology approaches fundamental scaling limits novel nanotechnologies offer great promise for VLSI integration at nanometer scales. The memristor, or memory resistor, is a novel nanoelectronic device that holds great promise for continued scaling for emerging applications. Memristor behavior is very similar to that of the synapses necessary for realizing a neural network. In this research, we have considered circuits that leverage memristance in the realization of an artificial synapse that can be used to implement neuromorphic computing hardware. A charge sharing based neural network is described which consists of a hybrid of conventional CMOS technology and novel memristors. Results demonstrate that the circuit can be implemented with energy consumption on the order of tens of femto-joules. Furthermore, a training circuit is presented for implementing supervised learning in hardware with low area overhead.

The recently discovered memristor has the potential to be the building block of a high-density memory system. A memristor based crossbar memory system was analyzed in terms of timing and switching energy using SPICE. The memristor model in the simulations was designed to match the I-V characteristics of three different published devices. The simulation results for each device were compared to demonstrate the performance of a one transistor one memristor (1T1M) memristor crossbar.

As conventional CMOS technology approaches fundamental scaling limits novel nanotechnologies offer great promise for VLSI integration at nanometer scales. The memristor, or memory resistor, is a novel nanoelectronic device that holds great promise for continued scaling for emerging applications. Memristor behavior is very similar to that of the synapses necessary for realizing a neural network. In this research, we have considered circuits that leverage memristance in the realization of an artificial synapse that can be used to implement neuromorphic computing hardware. A novel charge sharing based neural network is described which consists of a hybrid of conventional CMOS technology and novel memristors. Simulation results are presented which demonstrate that dense CMOS-memristive neural networks can be implemented with energy consumption on the order of tens of femto-joules.

We are pursuing an investigation of neuromorphic computational models and architectures in order to leverage present understanding of how the estimated 1011neurons and 1015neuron connections in the mammalian brain are able to do some of the things a human does, and as quickly as it does it, using slow base components, while consuming very little power on affordable synthetic non-biological computing hardware. Understanding and harvesting neurologically based methods is a promising approach with great potential that may help us achieve massively parallel computation far beyond the scope of traditional computing.

The value memristor devices offer to the neuromorphic computing hardware design community rests on the ability to provide effective device models that can enable large scale integrated computing architecture application simulations. Therefore, it is imperative to develop practical, functional device models of minimum mathematical complexity for fast, reliable, and accurate computing architecture technology design and simulation. To this end, various device models have been proposed in the literature seeking to characterize the physical electronic and time domain behavioral properties of memristor devices. In this work, we analyze some promising and practical non-quasi-static linear and non-linear memristor device models for neuromorphic circuit design and computing architecture simulation.

A model of portions of the cerebral cortex is being developed to explore neuromorphic computing strategies in the context of highly parallel platforms. The interest is driven by the value of applications which can make use of highly parallel architectures we expect to see surpassing one thousand cores per die in the next few years. A central question we seek to answer is what the architecture of hyper-parallel machines should be. We also seek to understand computational methods akin to how a brain deals with sensing, perception, memory, and cognition. The model is being developed incrementally, starting with the primary visual cortex (V1) field. It is based upon structures roughly corresponding to neocortical minicolumn and functional column structures. Gaps in neuroscience, such as inter-cell connectivity, are filled using estimates of functionality that are plausible given current understanding of the micro-anatomy. The success we encountered with achieving real-time performance is evidence validating the use of Cell-Be architecture in some classes of neuromorphic emulation. In this study we identified a particular gap-fill algorithm for lateral connections within V1 that is suggestive of a learning strategy whereby the lateral network subsumes expectation affect, reducing perception time and improving perception affect.