Vision Transformers (ViTs) often struggle to effectively capture local features. SpectFormer addresses this limitation by incorporating spectral blocks into the shallow layers of DeiT. However, deploying SpectFormer on edge devices is challenging due to its high computational complexity, the implementation of spectral blocks, additional matrix transpositions, and intensive nonlinear operations. To address these challenges, we propose an FPGA-based Frequency-focused Vision Transformer Accelerator (FFVTA), the first FPGA-based ViT accelerator that incorporates frequency-domain optimization for real-time inference of SpectFormer on edge devices. FFVTA employs a Unified DFT-Attention Matrix (UDAM) architecture to unify the computation of spectral and self-attention blocks, significantly enhancing the hardware reuse and reducing resource usage. Additionally, FFVTA introduces a Block-Broadcast Loop (BBL) Dataflow to efficiently accelerate matrix multiplication in self-attention blocks and a Configurable Two-Stage Log-Softmax (CTS-Log-Softmax) computation process to optimize nonlinear function computations. These innovations improve computational efficiency while reducing the resource usage. When deployed on a resource-constrained FPGA platform (KV260), FFVTA achieves a 16.61× speedup compared to the baseline, with significant reductions in the hardware resource usage and power consumption. FFVTA demonstrates superior performance with an energy efficiency of 63.40 GOPs/W and a DSP efficiency of 0.46 GOPs/DSP. FFVTA not only achieves efficient acceleration for the hierarchical SpectFormer-H-S variant, but also attains competitive accuracy of 84.02% on ImageNet classification.

This paper presents a compact 11-bit source driver for mobile OLED displays to achieve high uniformity. The proposed driver consists of a 5-bit high voltage resistor string digital to analog converter (HV-RDAC), a 6-bit low voltage resistor string digital to analog converter (LV-RDAC), and a switch capacitor adder (SC-Adder). This one-stage 11-bit hybrid DAC only needs 544 transistors, resulting in a true 10-bit display effect after gamma correction. The area of the proposed 11-bit source driver is only 36.8% of that of the conventional 8-bit high-voltage source driver. Furthermore, a capacitor-exchange method is introduced to address the non-uniformities among channels caused by capacitor mismatches. As a result, the maximum deviations of voltage outputs (DVOs) between 60 channels are 3 mV (without the capacitor-exchange method) and 1.5 mV (with the capacitor-exchange method). The worst differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.63 and 0.62 LSB respectively.

This paper demonstrates a highly reliable active pixel sensor (APS) based on dual-gate (DG) thin-film transistors (TFTs) for high-frame-rate dynamic X-ray medical imaging. By storing the threshold voltage (VT) in the auxiliary gate capacitor and amplifying the voltage signal through the primary gate electrode, the proposed APS circuit compensates for both positive and negative VTshifts of the amplifying TFT. Furthermore, using correlated double sampling by successively subsampling the same pixel without additional memory, the APS circuit eliminates low-frequency noise and DC offset, thereby effectively increasing the dynamic range and the signal-to-noise ratio. The charge-to-current gain of the proposed circuit is 4.50 μA/pC with a nonlinearity of 1.02%. Compared with the conventional 3-T pixel, the proposed APS features a decreased voltage error rate from 23.85% to 0.88% with a VTshift of ±1 V.

In-Sensor computing has emerged as a promising approach for fast, energy-efficient visual perception. This paper presents an in-sensor computing system that leverages amorphous metal oxide thin-film transistors (TFTs) for photo-sensing, computation, and control, enabling rapid and precise visual processing. The system directly computes the first layer of a neural network (NN) during exposure and supports high-resolution raw image readout once a target of interest is detected. The pixel circuit incorporates threshold voltage (VTH) compensation to ensure computational accuracy. Validated on the MNIST dataset, the system achieves 88% classification accuracy with only a 2.2% degradation under a 2V VTHshift. Post-Simulation results show that one computation frame can be finished within 500 ns, demonstrating a 20× speed enhancement over state-of-the-art silicon-based solutions.

This paper presents a highly robust -4V DC-DC converter composed of low-temperature poly-Si oxide (LTPO) TFTs. The proposed circuit significantly reduces the off-state overdrive voltage using the negative voltage bootstrapping technique, thus enhancing the circuit robustness in against VTHshifts for flexible applications. A dual-gate feedback is adopted in the loop control system for a reliable and constant output performance. The post-layout simulation results demonstrate that the steady-state voltage deviation remains below 1%, whereas the conventional design suffers from a voltage degradation of 17.1% for a VTHshift of ±3 V. Furthermore, the compact DC-DC converter achieves maximum power efficiency of 93.7% @20 μA, and 84.1% @100 μA.

This paper presents a capacitive sensing circuit for high-throughput active-matrix (AM) thin-film transistor (TFT) digital microfluidic (DMF) chips, with highly parallel operations to reduce frame time and thereby enhance chip throughput. The proposed circuit integrates a capacitance-to-frequency converter (CFC) into each DMF cell column, enabling simultaneous capacitance sensing and readout of DMF cells in the same row. Furthermore, a pipelined control scheme is devised to parallelize operations across rows, reducing frame time by over 81% compared to conventional DMF chips. Integrated with double-gate (DG) unipolar n-type amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs, the proposed circuit achieves a sensitivity of 13.06 kHz/pF and a resolution of 7.2 fF for a DMF array scale of 150 × 300.

An on-chip compensation system which is composed of an analog voltage adder and an 8-bit R-C digital-to-analog converter (DAC) is proposed for active matrix organic light-emitting diode (AMOLED) display drivers. The proposed analog voltage adder uses two groups of rail-to-rail input MOSFETs, which can work alternately, thereby extending the effective driving time (EDT) to 100%. The 8-bit R-C DAC is composed of a 5-bit R-DAC and a 3-bit C-DAC. The 3-bit C-DAC shares the capacitors with the analog voltage adder, reducing the layout area by 65% compared to the conventional method. This work is implemented in an industrial 0.18-μm CMOS technology. The measurement results show that the maximum INL of the system is 0.254 LSB, while the maximum DNL is 0.506 LSB. The layout area is only 9180 μm2per channel.

A compact low-voltage segmented digital to analog (D/A) converter with adjustable gamma correction coefficient is proposed for source drivers of active matrix organic light-emitting diode (AMOLED) displays. The shared resistor-string is separated into several segments. The switching networks for each segmentation could be realized using low-voltage or mediumvoltage transistors. The outputs of the segmented DACs are added up by an analog adder to obtain the final DAC value. Compared to the conventional resistor string DAC (R-DAC) with high-voltage transistors, the proposed D/A converter features the layout area reduction by 84.7%, due to the elimination of high-voltage transistors. The proposed segmented DAC is implemented in an industrial 0.25-μm CMOS technology. The measurement results show that the differential and integral nonlinearity of the proposed D/A converter are 0.21 LSB and 1.31 LSB, respectively, which are significantly lower compared to the previously published high resolution DACs. The deviation of output voltages is also reduced by up to 2.9× compared to the previously published high resolution DACs.