Hardware security is no longer a "nice to have" capability; it is required for many types of designs. Ensuring security is mandatory as part of the chip development process. Chip designers must take security into account and verification engineers must check that no vulnerabilities exist in the RTL design. Synopsys provides unparalleled functionality in this domain. This talk covers security overview for hardware, design and verification needs for secure semiconductors and briefs security verification solutions that Synopsys offers.

NIST selected ASCON as the standard Lightweight Cryptography (LWC) algorithm in 2023. ASCON’s implementations promise bringing lightweight Authenticated Encryption (AEAD) to resource-constrained devices surpassing Advanced Encryption Standard (AES) implementations. In this work, a standard compliant ASCON Application Specific Integrated Circuit (ASIC) hardware (HW) is designed and fabricated using CMOS GF22FDx technology. This study provides a quantitative assessment of the HW with two other standard compliant implementations of ASCON. One is software implementation (SW), and the other is a hardware accelerated (HW/SW co-design) implementation. The assessment shows that HW outperforms the SW implementation by up to three orders of magnitude in energy efficiency and throughput, whereas HW/SW co-design throughput and energy efficiency falls in the middle between HW and software. ASCON ASIC HW is also compared with a standard HW implementation of the AES fabricated over the same chip. ASCON uses only 39% of AES’s area and boosts energy efficiency by up to 25 times. To the best of our knowledge, this work is the first work providing a silicon-based analysis for ASCON ASIC implementation reaching a throughput of 4.3 Gbps @ 0.8V and 2 Gbps @ 0.6V, and energy efficiency of 1.9 Tb/J @ 0.8V and 3.5 Tb/J @ 0.6V in$2505~\mu $m2 on GF22FDx at 620MHz @ 0.8V. Furthermore, the comparative assessments between different implementations of ASCON guides the implementation choice for specific deployments to meet the demands of secure processing in dust-size sensors, edge and IoT.

Systems on Chips (SoCs) are integral to modern devices, from consumer electronics to critical applications in healthcare, finance, and defense, housing various vital assets. Ensuring comprehensive security verification is crucial to protect these assets from diverse vulnerabilities. However, traditional security verification is time-consuming, and the rapid pace of market-driven design cycles demands new versions within tight time-to-market windows. Conducting exhaustive security verification from scratch for each new design iteration is both challenging and impractical. This paper introduces a novel framework leveraging large language models (LLMs) to translate security properties from legacy designs to new versions at the Register Transfer Level (RTL). By reusing existing verification efforts, this approach significantly reduces verification time while maintaining security continuity. Our methodology not only trans-lates but also extends and expands security properties to detect new vulnerabilities. Experimental results demonstrate substantial improvements in security continuity and vulnerability detection, advancing hardware security verification for evolving SoCs.

Hardware security creates a hardware-based security foundation for secure and reliable operation of systems and applications used in our modern life. The presence of design for security, security assurance, and general security design life cycle practices in product life cycle of many large semiconductor design and manufacturing companies these days indicates that the importance of hardware security has been very well observed in industry. However, the high cost, time, and effort for building security into designs and assuring their security - due to using many manual processes - is still an important obstacle for economy of secure product development. This paper presents several promising directions for automation of design for security and security assurance practices to reduce the overall time and cost of secure product development. First, we present security verification challenges of SoCs, possible vulnerabilities that could be introduced inadvertently by tools mapping a design model in one level of abstraction to its lower level, and our solution to the problem by automatically mapping security properties from one level to its lower level incorporating techniques for extension and expansion of the properties. Then, we discuss the foundation necessary for further automation of formal security analysis of a design by incorporating threat model and common security vulnerabilities into an intermediate representation of a hardware model to be used to automatically determine if there is a chance for direct or indirect flow of information to compromise confidentiality or integrity of security assets. Finally, we discuss a pre-silicon-based framework for practical and time-and-cost effective power-side channel leakage analysis, root-causing the side-channel leakage by using the automatically generated leakage profile of circuit nodes, providing insight to mitigate the side-channel leakage by addressing the high leakage nodes, and assuring the effectiveness of the mitigation by reprofiling the leakage to prove its acceptable level of elimination. We hope that sharing these efforts and ideas with the security research community can accelerate the evolution of security-aware CAD tools targeted to design for security and security assurance to enrich the ecosystem to have tools from multiple vendors with more capabilities and higher performance.

Current cryptographic algorithms are designed for server environments prioritizing security with no limitations on hardware resources. They may not be suitable for emerging resource-constrained devices used in areas such as Edge computing, UAV, and IoT. For such constrained devices, many LWC algorithms have been proposed, however, there is no FIPS standard yet. So, NIST initiated a standardization process for a LWC FIPS standard. Finalists are announced with 10 algorithms after two rounds of evaluation. The aim of this work is to design and evaluate the hardware of these candidates using ASIC synthesis over GF 22nm CMOS technology. The evaluation focuses on energy efficiency using bit/joule as the main metric. Other metrics such as throughput and area are evaluated as well. Results show a great discrepancy in the energy efficiency between the finalists. For example, TinyJambu, Xoodyak and ASCON achieved 10-25 times better energy efficiency compared to ISAP, Elephant, and Grain-128AEAD while processing the same number of bits.

Parallelism and pipelining are widely used to improve the performance and throughput of systems. However, its effect on energy consumption needs to be studied. In this paper the alteration in energy consumption that results from using parallel architecture is studied over LWC algorithms from NIST standardization process. Ten algorithms are currently in the final round of the standardization process. Two algorithms out of the ten final round candidates can be parallelized which are Elephant and ISAP algorithms. For these algorithms, both iterative looping and parallel architectures are designed and synthesized over ASIC GF22nm technology. Then both architectures are compared in terms of area, throughput and energy. Results showed an enhancement in energy efficiency up to 49% and 28% and throughput improvement reaches up to 96% and 45% in Elephant and ISAP, respectively.

High-level synthesis (HLS) is essential to map the high-level language (HLL) description (e.g., in C/C++) of hardware design to the corresponding Register Transfer Level (RTL) to produce hardware-independent design specifications with reduced design complexity for ASICs and FPGAs. Adopting HLS is crucial for industrial and government applications to lower development costs, verification efforts, and time-to-market. Current research practices focus on optimizing HLS for performance, power, and area constraints. However, the literature does not include an analysis of the security implications carried through HLS-generated RTL translations (e.g., from an untimed high-level sequential specification to a fully scheduled implementation). This article demonstrates the evidence of security vulnerabilities that emerge during the HLS translation of a high-level description of system-on-chip (SoC) intellectual properties to their corresponding RTL. The evidence provided in this manuscript highlights the need for (a) guidelines for high-level programmers to prevent these security issues at the design time and (b) automated HLS verification solutions that cover security in their optimization flow.

BISTLock is a recently proposed logic-locking technique that integrates a barrier finite-state-machine (FSM) with the built-in self-test (BIST) controller. We demonstrate the vulnerability of BISTLock to removal/bypass attacks and develop countermeasures to make it resilient against not only removal attacks but any form of Oracle-guided attack. Removal resilience is achieved through the incorporation of an input-signal scrambler. We demonstrate the vulnerability of the standalone scrambler to the SAT attack and present a reconfigurable LFSR-based dynamic authenticator that achieves SAT resilience. The proposed solution provides dynamic obfuscation upon the application of an incorrect key and prevents Oracle access to the attacker. We also present a security analysis of the overall system against Oraclefree attacks such as BMC-based sequential SAT and the FSM reverse engineering attack. We evaluate the security strength of the proposed solution and show that hardware overhead is low for a broad set of benchmark circuits.

Although hardware security has received significant attention in the past decade or so, security design and validation engineers and researchers in industry, academia, and government have not still been equipped with a mature security-aware toolset to automatically and effectively analyze designs for various types of security vulnerabilities at different to detect and fix the security issues or build security in designs efficiently and easily. Despite such a demand, currently, there is not an ecosystem of security-aware Electronic Design Automation (EDA) or Computer-Aided Design (CAD) tools whereas the commercial design for security and validation tools are still in their infancy. However, there exist many research works that try to come up with security analysis engines and provide solutions to address different classes of security issues such as data leakage, access control violation, side-channel leakage, hardware Trojans and malicious changes, and vulnerabilities to physical attacks, fault-injection attacks, reverse engineering attacks, and chip counterfeiting or overproduction attacks. This paper presents the foundation established by several academic and industry researchers who have been supporting the realization of an ecosystem of security-aware CAD tools with their focus on hardware security coverage and fault-injection assessment for SoC designs, and security assurance standardization for electronic design integration.

International Microprocessor/SoC Test, Security and Validation (MTV) Workshop intends to bring researchers and practitioners from the fields of verification, security and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in security and verification and vice versa. This year are going to hold the 20th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross- examination of test, security and verification experiences and innovative solutions. This paper provides an overview of this workshop.

International Verification and Security Workshop intends to bring industry practitioners and researchers from the fields of security, verification, validation, test, and reliability to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us in various SOC design environments. It is sponsored by IEEE Council on Electronic Design Automation (CEDA). This paper provides an overview of this workshop.

The IP session focuses on challenges, opportunities, and solutions to hardware security. The first contribution discusses design for security and security validation challenges needed to be considered by EDA industry. The second presentation then talks about security verification technologies throughout the design lifecycle. The last contribution discusses a solution that can improve the security of electronic hardware manufacturing.