Mobile devices, especially smartphones, can support rich functions and have developed into indispensable tools in daily life. With the rise of generative AI services, smartphones can potentially transform into personalized assistants, anticipating user needs and scheduling services accordingly. Predicting user intents on smartphones, and reflecting anticipated activities based on past interactions and context, remains a pivotal step towards this vision. Existing research predominantly focuses on specific domains, neglecting the challenge of modeling diverse event sequences across dynamic contexts. Leveraging pre-trained language models (PLMs) offers a promising avenue, yet adapting PLMs to on-device user intent prediction presents significant challenges. To address these challenges, we propose PITuning, a Population-to-Individual Tuning framework. PITuning enhances common pattern extraction through dynamic event-to-intent transition modeling and addresses long-tailed preferences via adaptive unlearning strategies. Experimental results on real-world datasets demonstrate PITuning's superior intent prediction performance, highlighting its ability to capture long-tailed preferences and its practicality for on-device prediction scenarios.

Complex application specific SoC are being developed for hardware support artificial intelligence (AI) applications. Such a complex SoCs are integrating a large number of on-chip and off-chip memories, numerous cores and interfaces including in our case a hierarchy of embedded TAPs, as well as security measures and Design-For-Test (DFT) structures. In this case-study paper, we demonstrate using IEEE 1687-2014 (IJTAG) to integrate all these different components into a single, unifying methodology. From this, we derive the benefits of workflow efficiency and fast silicon bring-up. For example, we can report that silicon bring-up of the DFT of the entire SoC was completed in about 4 days, and other bring-up aspects of the Soc were also completed in very little time.

Recent advances in artificial intelligence (AI) are becoming a driving force behind the technological revolution and industrial transformation leading to economic and social development. Application specific AI SoCs are being developed at different companies to accelerate processing of the data-intensive AI computations. There are many new challenges in designing and implementing Design-For-Test (DFT) logic for AI SoCs. In this paper, we share our experiences with DFT implementation for our AI SoC. To achieve lower power and higher bandwidth for AI SoC, we use high speed Serdes PHY with lower threshold voltage, which uses many SoC pins. Therefore, it has a negative impact on DFT and ATPG due to lack of reusable IOs that can be used as scan test channels. In this paper, we present our solution and tradeoffs made to optimize DFT silicon area overhead, test cost, test coverage, pre-silicon verification run time with ready-to-use silicon bring-up methodologies.