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Mohamad Ali Mehrabi

dblp:221/5571 · also Mohammad Ali Mehrabi · DBLP profile ↗
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4ranked-venue papers
3as first author
3since 2021 · last 2023
0000-0003-3984-5361ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021Computer networks · 2 · 2 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 62% Integrated circuit design · 38%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis › public-key cryptography
elliptic curve cryptography
0.412020
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module · IEEE Trans. Computers 2020
Cryptographic primitives and cryptanalysis › public-key cryptography › elliptic curve cryptography
scalar multiplication
0.412020
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module · IEEE Trans. Computers 2020
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.412020
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module · IEEE Trans. Computers 2020
Integrated circuit design
digital circuit design
0.112020
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module · IEEE Trans. Computers 2020
Integrated circuit design
residue number system arithmetic
0.112020
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module · IEEE Trans. Computers 2020

Methods — techniques the papers use, named apart from their topics

residue number system · 0.9FPGA implementation · 0.9
YearPublicationVenuePosition
2023 Edge enhanced deep learning system for IoT edge device security analytics
abstract
Abstract The processing of locally harvested data at the physically accessible edge devices opens a new avenue of security threats for edge enhanced analytics. Cryptographic algorithms are used to secure the data being processed on the edge device. However, the implementation weakness of the algorithms on the edge devices can lead to side‐channel attack vulnerability, which is exacerbated with the application of machine‐learning techniques. This research proposes a deep learning‐based system integrated at the edge device to identify the side‐channel leakages. To design such a deep learning‐based system, one of the challenges is formulating the suitable attack model for the underlying target algorithm. Based on the previous findings, three machine learning‐based side‐channel attack models are curated and investigated for the edge device security evaluations. As a test case, the standard elliptic‐curve cryptographic algorithm is selected. Moreover, quantitative analysis is provided for the best attack model selection using standard machine‐learning evaluation metrics. A comparative analysis is performed on the raw unaligned data samples and reduced feature‐engineered samples using edge enhanced security analytics. The investigation concludes that the vulnerable algorithm implementation can lead to the secret key recovery from the edge device, with 96% accuracy, using a neural‐network‐based algorithm to analyse side‐channel attacks.
Naila Mukhtar, Mohamad Ali Mehrabi, Yinan Kong, Ashiq Anjum
Concurr. Comput. Pract. Exp.2
2022 Efficient Cryptographic Hardware for Safety Message Verification in Internet of Connected Vehicles
abstract
An important security requirement in automotive networks is to authenticate, sign, and verify thousands of short messages per second by each vehicle. This requirement mandates the use of a high speed Elliptic Curve Cryptography (ECC) hardware. The Residue Number Systems (RNS) provide a natural parallelism and carry-free operations that could speed-up long integer arithmetics of cryptographic algorithms. In this article, we propose a high-speed RNS Montgomery modular reduction units with parallel computing to reduce the latency of the field modular operations. We propose a fully RNS-based ECC scalar multiplication co-processor for NIST-P256r1 and Brainpool256r1 standard curves and improved the scalar multiplication speed using NAF and DBC numbering systems. Compared to the literature, our scheme provides faster computation without compromising the security level. The performance of our fully RNS-ECC point multiplication meets the requirements of the automotive industry.
Mohamad Ali Mehrabi, Alireza Jolfaei
ACM Trans. Internet Techn.1
2021 Power Side-Channel Analysis of RNS GLV ECC Using Machine and Deep Learning Algorithms
abstract
Many Internet of Things applications in smart cities use elliptic-curve cryptosystems due to their efficiency compared to other well-known public-key cryptosystems such as RSA. One of the important components of an elliptic-curve-based cryptosystem is the elliptic-curve point multiplication which has been shown to be vulnerable to various types of side-channel attacks. Recently, substantial progress has been made in applying deep learning to side-channel attacks. Conceptually, the idea is to monitor a core while it is running encryption for information leakage of a certain kind, for example, power consumption. The knowledge of the underlying encryption algorithm can be used to train a model to recognise the key used for encryption. The model is then applied to traces gathered from the crypto core in order to recover the encryption key. In this article, we propose an RNS GLV elliptic curve cryptography core which is immune to machine learning and deep learning based side-channel attacks. The experimental analysis confirms the proposed crypto core does not leak any information about the private key and therefore it is suitable for hardware implementations.
Mohamad Ali Mehrabi, Naila Mukhtar, Alireza Jolfaei
ACM Trans. Internet Techn.1
2020 Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module
abstract
In today's technology, a sheer number of Internet of Things applications use hardware security modules for secure communications. The widely used algorithms in security modules, for example, digital signatures and key agreement, are based upon elliptic curve cryptography (ECC). A core operation used in ECC is the point multiplication, which is computationally expensive for many Internet of things applications. In many IoT applications, such as intelligent transportation systems and distributed control systems, thousands of safety messages need to be signed and verified within a very short time-frame. Considerable research has been conducted in the design of a fast elliptic curve arithmetic on finite fields using residue number systems (RNS). In this article, we propose an RNS-based ECC core hardware for the two families of elliptic curves that are short Weierstrass and twisted Edwards curves. Specifically, we present RNS implementations for SECP256K1 and ED25519 standard curves. We propose an RNS hardware architecture supporting fast elliptic curve point-addition (ECPA), point-doubling (ECPD), and point-tripling (ECPT). We implemented different ECC point multiplication algorithms on the Xilinx FPGA platform. The test results confirm that the performance of our fully RNS ECC point multiplication is better than the fastest ECC point multiplication cores in the literature.
Mohamad Ali Mehrabi, Christophe Doche, Alireza Jolfaei
IEEE Trans. Computers1