This paper presents an energy-efficient low-noise dynamic comparator with a passive charge-pump pre-amplifier (CPP). We demonstrate the effectiveness of a passive pre-amplifier, cascaded to a dynamic comparator, to reduce input referred noise (IRN) of the comparator by a factor of pre-amplifier gain. Furthermore, the passive pre-amplifier, originating from a switched-capacitor amplifier, consumes only switching power, making it less burdensome to add it to the dynamic comparator. The proposed dynamic comparator, designed in a 180-nm CMOS process, achieves 37.1 µV of IRN, 817 fJ of energy per conversion under a 1.2-V supply, and a sampling frequency of 80 kHz. This results in a figure-of-merit of 1.12 nJ·µV2.

Despite the energy efficiency of memory-centric deep neural network (DNN) computations, the nonlinearities inherent in existing processing-in-memory (PIM) architectures cause severe accuracy drops. These imperfections necessitate additional methods to correct inaccurate vector-matrix multiplication (VMM) results. To address this issue without modifying DNN weights, we first propose an input sparsity-based error compensation method. This approach dynamically corrects accumulated errors along the column direction of the non-volatile memory (NVM) array using pre-collected errors and input characteristics. We then present a new PIM architecture along with the proposed compensation scheme by slightly modifying the existing analog-to-digital converter (ADC) or adding a few extra rows to the NVM array. Experimental results show that the proposed work mitigates the nonlinear effects of various emerging memory cells, achieving near-ideal DNN accuracy with negligible hardware overheads.

The measurement of small variation of the bioZ having a substantially large baseline impedance is a great challenge, requiring a wide dynamic range (DR) and a high signal-to-noise ratio (SNR). This paper presents a new impedance measurement architecture based on Δ-ΔΣ modulator with capacitive-feedback baseline cancellation. The readout front-end (RFE) of the integrated circuit (IC) is configured with a first-order Δ-ΔΣ modulator and a feedback capacitive digital-to-analog converter (CDAC) that minimize the power consumption. The front-stage Δ-modulation allows to achieve a wide input DR of 30 kΩ by eliminating the large static baseline impedance with no static current consumption. It also mitigates the input-dependent noise characteristic of the current balancing instrumentation amplifier (CBIA) significantly. The current generator (CG) generates a square wave for the excitation current with a current magnitude ranging from 5 μApkto 100 μApkover a frequency range from 1 kHz to 1024 kHz. The chopping and dynamic element matching (DEM) techniques are adopted in the bandgap reference (BGR), CG, and current-DAC (IDAC) to mitigate their flicker noises, which dominate the signal bandwidth (<10 Hz). The proposed IC designed in a 180-nm CMOS process consumes only 7.64 μW for the I path of the RFE, achieving a maximum SNR of 97.7 dB.

This paper presents a 72-channel resistive-sensor interface integrated circuit (IC). The proposed IC includes 8 sensor oscillators and 8 time-to-digital converters (TDCs), and each set of a sensor oscillator and a TDC is time-multiplexed to measure from 9 sensors. Consequently, it attains impressive energy efficiency of 310 pJ per channel. Employing a time-domain interface approach, the IC directly converts sensor resistance into time, extending its measurement capabilities up to 10 MΩ. It also takes advantage of a high-energy-efficiency phase-locked loop (PLL), resulting in a high signal-to-quantization-noise ratio (SQNR) that reaches the intrinsic signal-to-noise ratio (SNR) of the sensor oscillator. This results in an effective number of bits (ENOB) of 9.3 bits when 310 pJ is consumed for each channel. The ENOB can be adjusted through external FPGA control, and the maximum ENOB achieved is 14.1 with an oversampling ratio (OSR) of 256. The proposed IC, designed and fabricated in a 180-nm CMOS process with an active area of 0.015mm2, consumes only 15.07 μW per channel, resulting in a channel-specific Walden figure of merit (FoM) of 0.48 pJ per conversion step. Furthermore, by adjusting the OSR, the IC achieves an outstanding Schreier FoM of 159.8 dB in scenarios requiring high resolution.

This paper presents a ΔΣ-modulator-based reconfigurable multimodal sensor interface integrated circuit (IC), offering a novel approach to the multimodal measurement of voltage, capacitive, and current signals. A direct-conversion structure is employed in the multimodal sensor interface, and its reconfigurable ΔΣ modulation scheme ensures compact die area, high energy efficiency, and enhanced dynamic range. Fabricated in a 180-nm CMOS process, the multimodal sensor interface achieves measured dynamic ranges of 70.6 dB, 97.8 dB, and 60.0 dB for voltage, capacitance, and current modes, with measured power consumptions of 22.2 μW, 23.0 μW, and 37.7 μW, respectively. The proposed system demonstrates significant improvements in the dynamic range relative to power consumption compared to other state-of-the-art multimodal sensor interface IC designs.

This paper presents a neural recording integrated circuit (IC) with a DC-coupled VCO-based continuous-time ΔΣ modulator with a novel input transistor ΔΣ digital-to-analog converter (DAC) technique. The input transistor operating as a transconductor is implemented in the form of a transistor DAC (TR-DAC) consisting of multiple transistors, which enables the ΔΣ operation according to the output digital code. Notably, this topology isolates the input from the feedback loop, resulting in exceptionally high input impedance. Furthermore, the input transistor itself functions as a ΔΣ DAC, eliminating the need for additional passive or active DAC components. Consequently, the proposed design significantly reduces area consumption, enabling its application to future scalable brain-machine-interface (BMI) systems. The proposed IC designed in a 0.18-µm CMOS process consumes only 4.7 µW with a bandwidth of 5.12 kHz. Thanks to its DC-coupling characteristics and small input parasitic capacitance, the design achieves a high input impedance of 1.26 GΩ. Furthermore, the chip occupies a compact area of 0.054 mm2per channel, while the input TR-DAC used as a ΔΣ DAC occupies only 0.008 mm2.

A super-high-resolution capacitance-to-digital converter (CDC) capable of reaching sub-aF capacitance resolution has been proposed. The CDC employs a continuous-time (CT) low-noise capacitance-to-voltage converter (CVC) followed by a high linearity bandpass$\Delta\Sigma$ADC$(\text{BP}-\Delta\Sigma \mathrm{M})$without frequency demodulation. By avoiding demodulation and utilizing a narrow-band sensing technique, the proposed CDC achieves a sub-aF capacitance resolution while expanding the input capacitance range through a coarse C-DAC calibration loop. The proposed circuit has been implemented in a$0.35-\mu \mathrm{m}$CMOS process with a 3.3 V power supply voltage. The CDC shows a capacitance resolution of 0.98$\text{aF}_{\text{rms}}$, with a capacitance range of 3.1 pF, while consuming 4.16 mW.