Demo Data from VLDB 2026 / reviewers in the wild / expert
Esmaeil Mohammadian Koruyeh
dblp:222/1569 · also Esmaeil Mohmmadian Koruyeh
· DBLP profile ↗
5ranked-venue papers
1as first author
1since 2021 · last 2025
0000-0002-6584-9086ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 since 2021Security and privacy · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
4 papers |
Hardware security and side channels · 80% Systems and software security · 20% | |
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Processor architecture and microarchitecture · 100% |
Topics — the 13 heaviest of 14, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
speculative execution |
1.4 | 3 | 2025 | SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025 SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation · DAC 2019 SpecCFI: Mitigating Spectre Attacks using CFI Informed Speculation · SP 2020 |
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution defense |
0.9 | 1 | 2025 | SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025 |
Hardware security and side channels › microarchitectural attacks
transient execution attack |
0.9 | 1 | 2025 | SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025 |
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre |
0.8 | 2 | 2020 | SpecCFI: Mitigating Spectre Attacks using CFI Informed Speculation · SP 2020 SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation · DAC 2019 |
Systems and software security › memory safety
control-flow integrity |
0.4 | 1 | 2020 | SpecCFI: Mitigating Spectre Attacks using CFI Informed Speculation · SP 2020 |
Hardware security and side channels
microarchitectural attacks |
0.4 | 1 | 2020 | SpecCFI: Mitigating Spectre Attacks using CFI Informed Speculation · SP 2020 |
Hardware security and side channels › hardware attack detection
microarchitectural attack detection |
0.4 | 1 | 2020 | PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron · MICRO 2020 |
Processor architecture and microarchitecture › branch prediction
neural branch prediction |
0.4 | 1 | 2020 | PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron · MICRO 2020 |
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack |
0.4 | 1 | 2019 | SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation · DAC 2019 |
Processor architecture and microarchitecture › speculative execution
secure speculation |
0.4 | 1 | 2019 | SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation · DAC 2019 |
Systems and software security
memory safety |
0.3 | 1 | 2025 | SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025 |
Systems and software security › memory safety › hardware-enforced memory safety
memory tagging |
0.3 | 1 | 2025 | SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025 |
Processor architecture and microarchitecture
branch prediction |
0.1 | 1 | 2020 | SpecCFI: Mitigating Spectre Attacks using CFI Informed Speculation · SP 2020 |
Methods — techniques the papers use, named apart from their topics
speculative address sanitization · 1.7control-flow integrity · 1.7ARM Memory Tagging Extension · 1.7speculation-aware hardware stack · 0.9performance monitoring counters · 0.9perceptron learning · 0.9hardware CFI extensions · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | SpecASan: Mitigating Transient Execution Attacks Using Speculative Address SanitizationabstractTransient execution attacks (TEAs), such as Spectre and Meltdown, exploit speculative execution to leak sensitive data through residual microarchitectural state.Traditional defenses often incur high performance and hardware costs by delaying speculative execution or requiring additional shadow structures and dynamic information flow tracking.In contrast, our approach models these attacks as violations of software-defined security contracts and enforces these contracts in hardware using existing features.We introduce Speculative Address Sanitization (SpecASan), which leverages ARM's Memory Tagging Extension (MTE) to extend memory safety protection from the committed path to the speculative path.When a speculative access does not pass the MTE tag comparison, this access is delayed until speculation resolves.This ensures that only validated accesses affect the microarchitectural state while preserving the performance benefits of speculation.When combined with Control-Flow Integrity (CFI) enforcement mechanisms, already supported by some hardware implementations, our evaluation shows that SpecASan effectively mitigates a broad class of transient execution attacks, including Spectre and Microarchitectural Data Sampling (MDS).Furthermore, SpecASan achieves this with low performance overhead and minimal hardware complexity, highlighting its practicality and efficiency. Saber Ganjisaffar, Esmaeil Mohammadian Koruyeh, Jason Zellmer, Hodjat Asghari Esfeden, Chengyu Song, Nael B. Abu-Ghazaleh |
ISCA | 2 |
| 2020 | PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with PerceptronabstractDetecting microarchitectural attacks is critical given their proliferation in recent years. Many of these attacks exhibit intrinsic behaviors essential to the nature of their operation, such as creating contention or misspeculation. This study systematically investigates the microarchitectural footprints of hardware-based attacks and shows how they can be detected and classified using an efficient hardware predictor. We present a methodology to use correlated microarchitectural statistics to design a hardware-based neural predictor capable of detecting and classifying microarchitectural attacks before data is leaked. Once a potential attack is detected, it can be proactively mitigated by triggering appropriate countermeasures.Our hardware-based detector, PerSpectron, uses perceptron learning to identify and classify attacks. Perceptron-based prediction has been successfully used in branch prediction and other hardware-based applications. PerSpectron has minimal performance overhead. The statistics being monitored have similar overhead to already existing performance monitoring counters. Additionally, PerSpectron operates outside the processor's critical paths, offering security without added computation delay. Our system achieves a usable detection rate for detecting attacks such as SpectreV1, SpectreV2, SpectreRSB, Meltdown, breakingKSLR, Flush+Flush, Flush+Reload, Prime+Probe as well as cache-attack calibration programs. We also believe that the large number of diverse microarchitectural features offers both evasion resilience and interpretability-features not present in previous hardware security detectors. We detect these attacks early enough to avoid any data leakage, unlike previous work that triggers countermeasures only after data has been exposed. Samira Mirbagher Ajorpaz, Gilles Pokam, Esmaeil Mohammadian Koruyeh, Elba Garza, Nael B. Abu-Ghazaleh, Daniel A. Jiménez |
MICRO | 3 |
| 2020 | SpecROP: Speculative Exploitation of ROP Chains
Atri Bhattacharyya, Andrés Sánchez, Esmaeil Mohammadian Koruyeh, Nael B. Abu-Ghazaleh, Chengyu Song, Mathias Payer |
RAID | 3 |
| 2020 | SpecCFI: Mitigating Spectre Attacks using CFI Informed SpeculationabstractSpectre attacks and their many subsequent variants are a new vulnerability class affecting modern CPUs. The attacks rely on the ability to misguide speculative execution, generally by exploiting the branch prediction structures, to execute a vulnerable code sequence speculatively. In this paper, we propose to use Control-Flow Integrity (CFI), a security technique used to stop control-flow hijacking attacks, on the committed path, to prevent speculative control-flow from being hijacked to launch the most dangerous variants of the Spectre attacks (Spectre-BTB and Spectre-RSB). Specifically, CFI attempts to constrain the possible targets of an indirect branch to a set of legal targets defined by a pre-calculated control-flow graph (CFG). As CFI is being adopted by commodity software (e.g., Windows and Android) and commodity hardware (e.g., Intel's CET and ARM's BTI), the CFI information becomes readily available through the hardware CFI extensions. With the CFI information, we apply CFI principles to also constrain illegal control-flow during speculative execution. Specifically, our proposed defense, SpecCFI, ensures that control flow instructions target legal destinations to constrain dangerous speculation on forward control-flow paths (indirect calls and branches). We augment this protection with a precise speculation-aware hardware stack to constrain speculation on backward control-flow edges (returns). We combine this solution with existing solutions against branch target predictor attacks (Spectre-PHT) to close all known non-vendor-specific Spectre vulnerabilities. We show that SpecCFI results in small overheads both in terms of performance and additional hardware complexity. Esmaeil Mohammadian Koruyeh, Shirin Haji Amin Shirazi, Khaled N. Khasawneh, Chengyu Song, Nael B. Abu-Ghazaleh |
SP | 1 |
| 2019 | SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free SpeculationabstractSpeculative attacks, such as Spectre and Meltdown, target speculative execution to access privileged data and leak it through a side-channel. In this paper, we introduce (SafeSpec), a new model for supporting speculation in a way that is immune to the side-channel leakage by storing side effects of speculative instructions in separate structures until they commit. Additionally, we address the possibility of a covert channel from speculative instructions to committed instructions before these instructions are committed. We develop a cycle accurate model of modified design of an x86-64 processor and show that the performance impact is negligible. Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh |
DAC | 2 |