Manual sizing of analog circuit specifications has become challenging owing to their ever-increasing complexity. Especially for innovative, large-scale circuit designs with numerous design variables, operating conditions, and conflicting objectives to optimize, analog designers must run time-consuming simulations for several weeks to find the optimum configuration. Recently, machine learning and optimization techniques have been applied in the field of analog circuit design, wherein evolutionary algorithms and Bayesian models have shown good results for circuit sizing tasks. In this context, we introduce multi-objective optimization based on differential evolution and Bayesian inference (MODEBI)—a design optimization method based on generalized differential evolution 3 (GDE3) and Gaussian processes (GPs). The proposed method can perform sizing for complex circuits that require optimization of many design variables and conflicting objectives. Although state-of-the-art methods reduce multi-objective problems to single-objective optimization and potentially induce a priori bias, the proposed method searches directly over the multi-objective space using Pareto dominance and ensures that designers are provided with diverse solutions to choose from. To reduce optimization time, we propose using GPs to model the circuit and employing this surrogate model to preselect candidates. However, this results in a more complex offspring selection process, and the diversity in population survival must be specifically addressed. This paper proposes several solutions to these problems, resulting in multiple MODEBI variations. To the best of our knowledge, this is the first method that specifically addresses solution diversity and simultaneously focuses on minimizing the number of simulations required to obtain feasible configurations. The evaluation performed on two voltage regulators with different complexity levels showed that the proposed offspring selection method and survival policy can obtain highly diverse feasible solutions considerably faster than GDE3 or Bayesian optimization-based algorithms.

There is a consistent dependence between integrated circuits (ICs) performance parameters and manufacturing process variations and capturing it at an early development phase represents a major ongoing topic in the semiconductor industry. Typically, this is addressed by the means of Monte Carlo (MC) simulations, where the device model parameters are randomly instantiated according to the technology variations based on a predefined nominal process. Thus, the resulted simulation data can only capture the effect of these variations. This offers little or no insight on the performance’s sensitivities to specific process variations or on the effect of altered statistical technology properties, as it may be the case of process drift or fab-to-fab migration. This article proposes a methodology for modeling the dependency of the device performances (i.e., electrical parameters—EPs) with the influential technology parameters (i.e., process control monitor parameters—PCMs), at an early stage (preSilicon). Using a set of standard MC co-simulations of PCM structures and the circuit schematics (to maintain consistent process variation), it employs a feature selection step to choose the influential PCMs and it trains a machine learning regression algorithm. Both are wrapped up in a Bayesian optimization (BO) framework to find the optimal feature set and the regression hyperparameters. The obtained regression model can explain the functional dependency of the EP on the influential PCMs. Thus, it directly enables sensitivity analysis (SA) to process variation and parametric yield prediction of the IC, as it will be illustrated for the case of an experimental Infineon Technologies product.