A major challenge with the practical deployment of Internet-of-Things (IoTs) is how to develop the high-quality code needed in order to produce robust and secure IoT devices. In other domains, high-level programming languages have shown to be efficient vehicles towards this. However, the very limited compute power provided by IoT devices have made it difficult to apply the same approach to IoT devices. The Cephalopode processor is an attempt at implementing a low power hardware device directly aimed at running a high-level functional language. By integrating many resource-heavy tasks like garbage collection and arbitrary precision arithmetic into dedicated hardware, the Cephalopode processor explores the hypothesis that high-level functional languages can be used even for low-power IoT devices. This paper presents the implementation and evaluation of the Cephalopode processor. We discuss the approach taken, the compiler and the architecture of the processor. We also describe the design process and design considerations. After implementation and synthesis we compare the processor to a conventional RISC-V processor running a functional language software environment. We also compare Cephalopode with running handwritten C code on the RISC-V processor.

Domain-specific hardware design has become increasingly attractive as single-thread performance improvement has drastically slowed down. At the same time, it is clear that traditional hardware design approaches are difficult and error-prone. In this paper we describe a hardware design language, Bifröst, aimed at allowing clear, correct, and modular specification of hardware. Bifröst is tightly integrated into the Thor system, and thus a design in Bifröst can be refined in a correctness-preserving way to a realistic hardware implementation. This paper gives both syntax and semantics of the language, highlights important design decisions, and illustrates its use in several projects.

The Internet of Things (IoT) conceives a future where "things" are interconnected by means of suitable information and communication technologies. Unfortunately, recent events have demonstrated the high vulnerability of IoT. One of the main reasons for this is the use of low-level programming languages. The Octopi project is developing technologies to easily and securely program IoT devices by the use of functional high-level languages. Unfortunately, a traditional implementation of a modern functional language that runs on traditional hardware is very resource demanding. So resource demanding that few, if any, IoT devices can run them.In the Cephalopode project (which is a subproject of Octopi) we are exploring the implementation of a very low power hardware device directly aimed at running a high-level functional language. By integrating many resource-heavy tasks into dedicated hardware, we aim at creating an execution engine for IoT devices that will allow secure programming.

Finite state machines (FSMs) are at the heart of many digital circuits, in particular microprocessors such as the IoT-oriented Cephalopode processor we are implementing as part of the Octopi project.We frequently encounter two practical difficulties with FSM design: first, in the case of Mealy machines state transitions and output logic can have complex and overlapping conditions, which are difficult to maintain and comprehend if separated; and second, there is a tension between clarity and clock cycles with respect to the insertion of intermediate states.To address these in the context of the Cephalopode processor we developed the open-source tool Stately, a visual environment for designing finite state machines. States are organized spatially, individually programmed in a simple domain-specific language, and the resulting machine can be compiled to HFL code for the VossII hardware design and simulation platform.In addition to allowing the intermingling of transitions and output declarations, Stately introduces a mechanism by which chosen states can be merged during compilation. While only a modest semantic extension, it resolves several clarity-efficiency tradeoffs while retaining a clear visual interpretation. Other features include lightweight simulation for rudimentary testing, and extensive error-checking.