Ordered statistics decoding (OSD) can achieve near maximum likelihood (ML) decoding performance for BCH codes. However, Gaussian elimination (GE) that delivers the systematic generator matrix of the code has an uncompromised latency. Addressing this challenge, this paper proposes a low-latency OSD (LLOSD) for BCH codes. Since BCH codes are binary subcodes of Reed-Solomon (RS) codes, codeword candidates can be produced using the RS systematic generator matrix, whose entries can be generated in parallel. By eliminating the non-binary codeword candidates and identifying the ML codeword, the LLOSD yields a lower latency as well as complexity than the OSD. It is shown that the LLOSD can be interpreted as generating the codeoword candidates through systematic encoding of a punctured BCH codeword, explaining its low-complexity feature. Moreover, the segmented variant is proposed to further facilitate the LLOSD. In order to decode long BCH codes, a hybrid soft decoding (HSD) is finally proposed. It integrates the LLOSD and the algebraic Chase decoding that can effectively provide extra TEPs for the LLOSD, enhancing the decoding performance. Both the complexity and performance of the proposed decoding are analyzed, demonstrating their advantage over the relevant state-of-the-art decoding.

Targeting high-throughput and low-power communications, we implement two successive cancellation (SC) decoders for polar codes. Converted to 16nm ASIC technology, the area efficiency and energy efficiency are 4Tbps/mm2and 0.63pJ/bit, respectively, for the unrolled decoder, and 561Gbps/mm2and 1.21pJ/bit, respectively, for the recursive decoder. To achieve such a high throughput, a novel code construction, coined as fast polar codes, is proposed and jointly optimized with a highly-parallel SC decoding architecture. First, we reuse existing modules to fast decode more outer code blocks, and then modify code construction to facilitate faster decoding for all outer code blocks up to a degree of parallelism of 16. Furthermore, parallel comparison circuits and bit quantization schemes are customized for hardware implementation. Collectively, they contribute to an 2.66× area efficiency improvement and 33% energy saving over the state of the art.

In this paper, we design a polar decoding platform for diverse application scenarios that require low-cost and low-power communications. Specifically, prevalent polar decoders such as successive cancellation (SC), SC-list (SCL) and Fano decoders are all supported under the same architecture. Unlike high-throughput or low-latency decoders that promote parallelism, this architecture promotes serialization by repeatedly calling a “sub-process” that is executed by a core module. Surprisingly, the resulting serial SCL-8 decoder is only 3 times the size of an SC decoder, much smaller than the predicted 8 times. Cost and power are minimized through resource sharing and adaptive decoding techniques, etc. We carried out performance simulation and hardware implementation to evaluate the actual chip area and energy consumption.

Recently, a parallel decoding algorithm of GN-coset codes was proposed. The algorithm exploits two equivalent decoding graphs. For each graph, the inner code part, which consists of independent component codes, is decoded in parallel. The extrinsic information of the code bits is obtained and iteratively exchanged between the graphs until convergence. This algorithm enjoys a higher decoding parallelism than the previous successive cancellation algorithms, due to the avoidance of serial outer code processing. In this work, we present a hardware implementation of the parallel decoding algorithm, it can support maximum N = 16384. We complete the decoder's physical layout in TSMC 16nm process and the size is 999.936μm×999.936μm, ≈ 1.00mm2. The decoder's area efficiency and power consumption are evaluated for the cases of N = 16384, K = 13225 and N = 16384, K = 14161. Scaled to 7nm process, the decoder's throughput is higher than 477Gbps/mm2and 533Gbps/mm2with five iterations.

Recently, a parallel decoding framework of GN-coset codes was proposed. High throughput is achieved by decoding the independent component polar codes in parallel. Various algorithms can be employed to decode these component codes, enabling a flexible throughput-performance tradeoff. In this work, we adopt successive cancellation (SC) as the component decoders to achieve the highest-throughput end of the tradeoff. The benefits over soft-output component decoders are reduced complexity and simpler (binary) interconnections among component decoders. To reduce performance degradation, we integrate an error detector and a log-likelihood ratio (LLR) generator into each component decoder. The LLR generator, specifically the damping factors therein, is designed by a genetic algorithm. This low-complexity design can achieve an area efficiency of 533Gbps/mm2under 7nm technology.

Polar codes has been selected as the channel coding scheme for 5G new radio (NR) control channel. Specifically, a special type of parity-check polar (PC-Polar) codes was adopted in uplink control information (UCI). In this paper, we propose a parity-check soft-cancellation (PC-SCAN) algorithm and its simplified version to decode PC-Polar codes. The potential benefits are two-fold. First, PC-SCAN can provide soft output for PCPolar codes, which is essential for advanced turbo receivers. Second, the decoding performance is better than that of successive cancellation (SC). This is due to the fact that paritycheck constraints can be exploited by PC-SCAN to enhance the reliability of other information bits over the iterations. Moreover, we describe a cyclic-shift-register (CSR) based implementation "CSR-SCAN" to reduce both hardware cost and latency with minimum performance loss.

In this work, we propose a type of GN-coset codes for parallel decoding. The parallel decoder exploits two equivalent decoding graphs of GN-coset codes. For each decoding graph, the inner code part is composed of independent component codes to be decoded in parallel. The extrinsic information of the code bits is obtained and iteratively exchanged between the two graphs until convergence. Accordingly, we explore a heuristic and flexible code construction method (information set selection) for various information lengths and coding rates. Compared to the previous successive cancellation algorithm, the parallel decoder avoids the serial outer code processing and enjoys a higher degree of parallelism. Furthermore, a flexible trade-off between performance and decoding latency can be achieved with three types of component decoders. Simulation results demonstrate that the proposed encoder-decoder framework achieves comparable error correction performance to polar codes with a much lower decoding latency.