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Kate Nguyen

dblp:223/7835 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2023
0000-0002-5380-9271ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 77% Hardware reliability and fault tolerance · 12% Storage systems · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
DRAM
0.312018
Nonblocking Memory Refresh · ISCA 2018
Memory systems › DRAM
DRAM refresh
0.312018
Nonblocking Memory Refresh · ISCA 2018
Hardware reliability and fault tolerance
error correction
0.112018
Nonblocking Memory Refresh · ISCA 2018
Storage systems › data representation › data encoding › error correction coding
reed-solomon codes
0.112018
Nonblocking Memory Refresh · ISCA 2018
YearPublicationVenuePosition
2023 Non-majors Explore Less Well-Known Contributors to Computing
abstract
A typical US college student who is asked to name people who have made significant contributions to computing will likely produce a short, predictable, fairly homogeneous list. To help increase awareness of the diversity of people involved in computing, we introduced a biography project into an introductory non-majors course at a small liberal arts college. With each student exploring and presenting on the life and contributions of a less well-known contributor to computing, the class is exposed to a number of people that students likely haven't heard of previously. Moreover, with fairly open-ended requirements for the assignment, we can learn what students find interesting and noteworthy about these individuals, perhaps finding ways to more broadly increase awareness.
Barbara M. Anthony, Kate Nguyen
SIGCSE (2)2
2018 Nonblocking Memory Refresh
abstract
Since its inception half a century ago, DRAM has required dynamic/active refresh operations that block read requests and decrease performance. We propose refreshing DRAM in the background without stalling read accesses to refreshing memory blocks, similar to the static/background refresh in SRAM. Our proposed Nonblocking Refresh works by refreshing a portion of the data in a memory block at a time and uses redundant data, such as Reed-Solomon codes, in the block to compute the block's refreshing/unreadable data to satisfy read requests. For proof of concept, we apply Nonblocking Refresh to server memory systems, where every memory block already contains redundant data to provide hardware failure protection. In this context, Nonblocking Refresh can utilize server memory system's existing per-block redundant data in the common-case when there are no hardware faults to correct, without requiring any dedicated redundant data of its own. Our evaluations show that on average across five server memory systems with different redundancy and failure protection strengths, Nonblocking Refresh improves performance by 16.2% and 30.3% for 16gb and 32gb DRAM chips, respectively.
Kate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, Xun Jian 0002
ISCA1