With the advent of next-generation networks, new applications across multiple domains are gaining traction. This shift demands a redefined network paradigm, where ultrareliable, low-latency communication is key. In this work, we explore and extend the concept of in-network programmability in new directions. Unlike conventional approaches, we leverage P4 data plane programmability to implement an in-network collision avoidance algorithm in a UAV scenario. We evaluate our hardware-based implementation under different conditions, including latency and velocity, demonstrating that it efficiently detects and prevents collisions. Our results show the impact of end-to-end latency and highlight how in-network processing can be a valuable ally for time-sensitive tasks, paving the way for future advancements in hardware-based in-network applications.

Remote Direct Memory Access (RDMA) is a key technology in modern data centers, enabling low-latency and high-throughput communication. However, evaluating RDMA performance and validating network designs often requires costly hardware setups or simulation tools with limited performance and realism. In this work, we present P4DMA, a system that leverages programmable switch ASICs to generate realistic high-performance RDMA traffic. By implementing RDMA traffic patterns using the P4 language, P4DMA enables researchers and practitioners to generate RDMA workloads at line rate, without relying on traditional RDMA NICs (RNICS). With Tofino's traffic generation capacity of up to Tbps, P4DMA offers a novel approach to stress and evaluate RDMA-capable infrastructures, and accelerate the prototyping of new RDMA-based applications.

Holographic-type communication demands multi-Gbps throughput and ultra-low latency, posing significant challenges to current 5G networks. This demo work presents a programmable testbed built on the P7 network emulator, which overcomes the throughput constraints of conventional platforms. Our demonstration deploys three edge computing slices—one at a far edge and two at near edges—to support volumetric media streaming directly to VR head-mounted display. By facilitating precise adjustment of network metrics such as latency and packet loss across the P7-enabled slices, the testbed allows users to visually observe the resulting effects on holographic content in VR. Although automated measurement of Quality of Experience (QoE) parameters are not incorporated, the testbed provides a valuable experimental environment where researchers can subjectively evaluate the relationship between network conditions and perceived quality, thereby gaining insights into optimizing network performance for enhanced Quality of Service (QoS).

The increasing demand for real-time industrial applications demands deterministic communication across networked devices. Time-sensitive networking (TSN) offers reliable performance to meet these requirements, compatible with the current Real-Time Ethernet (RTE) solutions applied in the industry. While TSN ensures determinism inside Ethernet networks, its integration with 5G/6G wireless technologies can overcome flexibility limitations. This paper explores key challenges in integrating TSN with mobile networks, focusing on device synchronization and flow mapping. We introduce a tool aligned with the 3GPP specifications that covers time synchronization across TSN domains via 5G and implements flow mapping based on application-specific quality of service (QoS) requirements. We evaluate these features under various scenarios, including a use case for an industrial production line use case. Our solution is developed as an open-source framework for the OMNeT++ simulator, supporting reproducibility and continuous updates and paving the way for customizable network solutions.

Accurate time synchronization is essential for emerging networked applications that demand low latency, high precision, and coordinated operations, such as those found in data centers, time-sensitive networking (TSN), and distributed systems. In this demo, we introduce P4Timely, a flexible and programmable framework designed to evaluate and prototype time synchronization protocols in real time. Built using P4 and commodity programmable hardware, P4Timely enables users to easily configure synchronization settings through a simple interface, specify network conditions such as delay, jitter, and packet loss, and define whether nodes act as synchronizing or synchronized entities. P4Timely supports dynamic reconfiguration at runtime and provides built-in monitoring tools to assess synchronization accuracy under diverse network conditions.

In recent years, the increasing demand for network resources due to real-time applications and data-intensive activities has posed challenges in managing and optimizing network performance. To assess network performance, security, and efficiency, traffic generation plays a crucial role. We introduce PIPO-TG, a Tofino-based traffic generation for high-performance experiments. The primary objective of PIPO-TG is to generate realistic and diverse traffic patterns, enabling researchers to evaluate network performance under varying conditions providing customizable packet forwarding with P4 programmable data planes. Our main contributions include user-defined packet header customization and open-source code for reproducibility. These efforts foster collaboration within the research community to advance traffic generation techniques. We show that PIPO-TG only requires a few lines of code to simulate heterogeneous network scenarios (e.g., traffic bursts and DDoS attacks) while maintaining hardware performance and flexibility.

Network emulation traditionally relies on software-based solutions. While extremely useful in many scenarios, it suffers from performance fidelity and inherent scalability constraints. With the advent of P4 and programmable switches like Tofino, new opportunities for hardware-based network emulation are emerging. P7 (P4 Programmable Patch Panel) offers a solution for high-fidelity 100G traffic network emulation, including different link characteristics such as latency, jitter, packet loss, and bandwidth, as well as the ability to define custom topologies. However, it currently lacks support for custom P4 code in emulated devices. This is where multiple pipelines network emulation comes in. In this demonstration, we show how to emulate a topology using P7 and incorporate custom P4 code into each emulated node. We allocate a dedicated pipe for user-defined P4 code and allow users to conFigure tables for each node separately.

In recent years, advances in virtual reality (VR) technologies (e.g., high-quality VR headsets) have enabled a new perspective of experiences for users (e.g., gaming, online events). However, ensuring the user experience is still a challenge. Existing solutions are limited to measuring and estimating QoE at the user plane (e.g., VR player) or at the control plane, imposing unfeasible latency for different scenarios (5G networks and beyond). In this work, we propose QoEyes, an in-network QoE estimation based on the use of Inter-Packet-Gap (IPG) in programmable devices. Our results show that the IPG measured on the data plane is strongly linked to QoE, yielding an accurate data plane QoE estimate.

Recent advances in VR technology have created new user experiences (e.g., online events, gaming). However, ensuring the user experience is still a challenge. Mostly because Quality of Experience (QoE) measurement is limited to the user or control plane, causing high latencies for different scenarios (e.g., 5G networks and beyond). To address this challenge, we present QoEyes, an in-network QoE estimation technique based on Inter-Packet-Gap (IPG) measured in programmable devices. Our results show that a strong estimate of the user’s QoE can be provided by measuring the IPG on the data plane. Additionally, in this demonstration, we show this QoE estimate and other related metrics in real time, using a Grafana dashboard running in our monitoring server.

Due to the advanced control and machine learning techniques, today's industrial robots are faster and more accurate than human workers in well-structured repetitive tasks. However, in case of sudden changes in the operational area, such as unexpected obstacles or humans, robots have to be continuously monitored by powerful controllers for swift interventions (i.e., send emergency stop signals). As in the case of many verticals (e.g., transportation, shopping), the proliferation of Software-Defined Networking (SDN) and Network Function Virtualization (NFV) has started to captivate industry 4.0 as well in order to benefit from low infrastructure costs, and flexible management and resource provisioning. Besides all the advantages of the centralized approach, however, in critical situations (e.g., possible collisions, actuator damages or human injuries) the required ultra-low latency between the robots and the controller becomes an all-important factor, and one of the main concerns, at the same time, for industry leaders making the decision towards this paradigm shift. In this paper, we argue that by relying on recently emerged stateful and programmable data planes, it is possible to fill this gap by offloading latency-critical applications to the network, thereby bringing some intelligence much closer the robots. We present the first in-network robotic control application that is capable to intercept the communication between the robot and the controller and craft responses immediately if needed. In particular, we show that we can detect position threshold violations entirely in the data plane, close to the robot, and deliver emergency stop commands within no time with full compliance to the actual TCP session and application states.

Despite having received less attention compared to the control and application plane aspects of software-defined networking (SDN), the data plane is a critical piece of the puzzle. P4 takes SDN datapaths to the next level by unlocking deep programmability through a target-independent high-level programming language that can be compiled to run on a variety of targets (e.g., ASIC, FPGA, and GPU). This paper presents the design and evaluation of our sweet spot approach on SDN datapaths, offering three contending characteristics, namely, performance, portability, and scalability in multiple realistic scenarios. The focus is on our Multi-Architecture Compiler System for Abstract Data Planes proposal, which blends the high-level protocol-independent programmability of P4 with low-level but cross-platform (HW & SW) Application Programming Interfaces brought by OpenDataPlane, this way supporting many different vendors and architectures. Besides the performance evaluation for varying packet sizes and memory lookup tables, we investigate the impact of increasing pipeline complexity ranging from elemental L2 switching to more complex data center and border network gateways. We investigate the scalability for increasing the number of cores and evaluate a novel method for run-time core reallocation. Furthermore, we run experiments on different target platforms (e.g., ×86, ARM, 10G/100G), inducing different ways of packet mangling through specific drivers (e.g., DPDK and Netmap), and compare the results to state-of-the-art datapath alternatives.