Sarbartha Banerjee

dblp:224/8745 · DBLP profile ↗
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4ranked-venue papers
1as first author
3since 2021 · last 2025
0009-0006-9704-932XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 2 · 2 since 2021Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 since 2021
YearPublicationVenuePosition
2025 SCALE-Sim V3: a Modular Cycle-Accurate Systolic Accelerator Simulator for End-To-End System Analysis
abstract
The rapid advancements in AI, scientific computing, and high-performance computing (HPC) have driven the need for versatile and efficient hardware accelerators. Existing tools like SCALE-Sim v2 provide valuable cycle-accurate simulations for systolic-array-based architectures but fall short in supporting key modern features such as sparsity, multi-core scalability, and comprehensive memory analysis. To address these limitations, we present SCALE-Sim v3 (GitHub Repository), a modular, cycle-accurate simulator that extends the capabilities of its predecessor. SCALE-Sim v3 introduces five significant enhancements: multi-core simulation with spatio-temporal partitioning and hierarchical memory structures, support for sparse matrix multiplications (SpMM) with layer-wise and row-wise sparsity, integration with Ramulator for detailed DRAM analysis, precise data layout modeling to minimize memory stalls, and energy and power estimation via Accelergy. These improvements enable deeper end-to-end system analysis for modern AI accelerators, accommodating a wide variety of systems and workloads and providing detailed full-system insights into latency, bandwidth, and power efficiency. A$128 \times 128$array is$6.53 \times$faster than a$32 \times 32$array for ViTbase, using only latency as a metric. However, SCALE-Sim v3 finds that$32 \times 32$is$2.86 \times$more energy-efficient due to better utilization and lower leakage energy. For EdP,$64 \times 64$outperforms both$128 \times 128$and$32 \times 32$for ViT-base. SCALE-Sim v2 shows a 21 % reduction in compute cycles for six ResNet18 layers using weight-stationary (WS) dataflow compared to outputstationary (OS). However, when factoring in DRAM stalls, OS dataflow exhibits 30.1% lower execution cycles compared to WS, highlighting the critical role of detailed DRAM analysis.
Ritik Raj, Sarbartha Banerjee, Nikhil Chandra, Zishen Wan, Jianming Tong, Ananda Samajdar, Tushar Krishna
ISPASS2
2023 Rethinking System Audit Architectures for High Event Coverage and Synchronous Log Availability
Varun Gandhi, Sarbartha Banerjee, Aniket Agrawal, Adil Ahmad, Sangho Lee 0001, Marcus Peinado
USENIX Security Symposium2
2022 Spacelord: Private and Secure Smart Space Sharing
abstract
Space sharing services like vacation rentals are being equipped with smart devices. However, sharing of such devices has privacy and security problems due to no or unclear control transfer between owners and users. In this paper, we propose Spacelord, a system to time-share smart devices contained in a shared space privately and securely while allowing users to configure them. When a user stays at a space, Spacelord ensures that the smart devices contained in it run code and configurations the user trusts while removing pre-installed code and configurations. When the user leaves the space, Spacelord reverts any changes the user has introduced to the smart devices to delete remaining private data and let the owner take back control over the devices. We evaluate Spacelord for two realistic space-sharing cases—smart home and coworking meeting room—and observe reasonable provisioning delay and runtime overhead.
Yechan Bae, Sarbartha Banerjee, Sangho Lee 0001, Marcus Peinado
ACSAC2
2018 Characterization of Smartphone Governor Strategies
Sarbartha Banerjee, Lizy Kurian John
Euro-Par1